KR960025070A - Bus Arbitration Between Multiple Bus Masters - Google Patents

Bus Arbitration Between Multiple Bus Masters Download PDF

Info

Publication number
KR960025070A
KR960025070A KR1019940040177A KR19940040177A KR960025070A KR 960025070 A KR960025070 A KR 960025070A KR 1019940040177 A KR1019940040177 A KR 1019940040177A KR 19940040177 A KR19940040177 A KR 19940040177A KR 960025070 A KR960025070 A KR 960025070A
Authority
KR
South Korea
Prior art keywords
bus
master
masters
priority
signal
Prior art date
Application number
KR1019940040177A
Other languages
Korean (ko)
Inventor
노병철
Original Assignee
구자홍
Lg 전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 구자홍, Lg 전자 주식회사 filed Critical 구자홍
Priority to KR1019940040177A priority Critical patent/KR960025070A/en
Publication of KR960025070A publication Critical patent/KR960025070A/en

Links

Landscapes

  • Bus Control (AREA)

Abstract

본 발명은 다중 버스 마스터간의 버스중재방법에 관한 것으로서, 종래 기술에서의 우선 순위가 낮은 마스터가 자신의 버스 사용순서가 올 때까지 대기하여야만 하는 문제점을 해결하기 위해 우선 순위가 다른 마스터의 버스 사용 요청이 동시에 여러번 일어났을 경우 우선 순위가 낮은 버스 마스터도 우선 순위가 높은 마스터와 동등하게 버스를 사용할 수 있도록 한 버스중재방법을 수행함으로써 우선 순위가 높은 마스터의 독점적 버스사용을 방지하고, 시스템의 스타베이션 타임아웃을 방지할 수 있으며, 마스터의 처리속도를 균등하게 하여 시스템의 안정성 확보 및 성능 개선 효과가 있다.The present invention relates to a bus arbitration method between multiple bus masters. In order to solve a problem in which a low priority master in the prior art has to wait for its bus usage order, a bus use request of a master having a different priority is different. In the event of multiple occurrences at the same time, a bus arbitration method is performed to ensure that even lower-priority bus masters can use buses on a par with higher-priority masters. Timeout can be prevented, and the processing speed of the master is equalized, thereby securing the stability of the system and improving performance.

Description

다중 버스 마스터간의 버스중재방법Bus Arbitration Between Multiple Bus Masters

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명 다중 버스 마스터간의 버스중재과정을 나타낸 흐름도.2 is a flowchart illustrating a bus arbitration process between multiple bus masters of the present invention.

Claims (1)

복수개의 마스터들이 동시에 버스 사용 요청을 하기 이전에 버스 사용 요청이 전혀 없거나 하나만 있을 경우인지의 판단을 위한 공정신호 셋팅유무를 판단하는 제1공정신호유무 판단과정과, 상기 공정신호유무 판단 과정으로 공정신호가 셋팅되어 있을 경우 버스 사용 요청신호인 마스터신호 구동 후 우선 순위에 따라 버스사용 중재를 하는 버스중재과정과, 상기 버스중재과정으로 버스 사용권을 얻은 버스 마스터의 사용 종류 후 자신의 마스터 신호를 클리어 시키는 버스 마스터 사이클 과정으로 이루어진 것을 특징으로 하는 다중 버스 마스터간의 버스중재방법.The first process signal determination process for determining whether there is no bus use request or if there is only one bus use request before the plurality of masters simultaneously request the bus use process, and the process is performed by the process signal determination process. If the signal is set, the bus arbitration process is arbitrated according to the priority after driving the master signal, which is the bus use request signal, and the master signal is cleared after the type of use of the bus master obtained by the bus arbitration process. Bus arbitration method between the multiple bus master, characterized in that consisting of a bus master cycle process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940040177A 1994-12-30 1994-12-30 Bus Arbitration Between Multiple Bus Masters KR960025070A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940040177A KR960025070A (en) 1994-12-30 1994-12-30 Bus Arbitration Between Multiple Bus Masters

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940040177A KR960025070A (en) 1994-12-30 1994-12-30 Bus Arbitration Between Multiple Bus Masters

Publications (1)

Publication Number Publication Date
KR960025070A true KR960025070A (en) 1996-07-20

Family

ID=66648061

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940040177A KR960025070A (en) 1994-12-30 1994-12-30 Bus Arbitration Between Multiple Bus Masters

Country Status (1)

Country Link
KR (1) KR960025070A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030066009A (en) * 2002-02-04 2003-08-09 엘지이노텍 주식회사 Structure and method for bus arbitration in multi master bus system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030066009A (en) * 2002-02-04 2003-08-09 엘지이노텍 주식회사 Structure and method for bus arbitration in multi master bus system

Similar Documents

Publication Publication Date Title
EP0347763A3 (en) Dual rotating priority arbitration method for a multiprocessor memory bus
ES2004366A6 (en) Apparatus and method responding to an aborted signal exchange between subsystems in a data processing system.
KR970049695A (en) Asymmetric Bus Arbitration Protocol
US5218702A (en) System for selecting request for a resource before decoding of requested resource address and validating selection thereafter
NO862764D0 (en) ARRANGEMENT FOR DIVISION OF PRIORITY BETWEEN COMPUTERS.
KR970007567A (en) Dual-Bus Riser Card Only for Expansion Slots
KR960025070A (en) Bus Arbitration Between Multiple Bus Masters
EP0811924A3 (en) Bus arbitration
US6105082A (en) Data processor used in a data transfer system which includes a detection circuit for detecting whether processor uses bus in a forthcoming cycle
TW353168B (en) Method and apparatus for improving fairness in SCSI bus arbitration
KR970066791A (en) How to Improve the Clock Speed of the System Bus in Multiprocessor Systems
CA2145553A1 (en) Multi-Processor System Including Priority Arbitrator for Arbitrating Request Issued from Processors
KR910008592A (en) Delay logic to prevent release of bus ownership of the CPU
KR940018763A (en) A method and apparatus for improving data transfer efficiency of multiple processors from memory in a data processing device.
KR910008593A (en) Interruption control for the central processor
KR960016243A (en) Multichannel SIOP bus arbitration method
KR970049648A (en) Variable Priority Bus Arbitration Method
KR930014078A (en) Bus arbitration method
JPH0293751A (en) Priority order determining system for right to use bus
KR960025053A (en) Master Arbitration Method of PCI Bus
KR940015855A (en) How to Improve Arbitration for Multi-Request Locking
KR970019230A (en) A coded self arbitration method for distributed arbitration of shard bus
JPH0436604U (en)
KR950020198A (en) How to Control System Bus Usage Between Multiple Processors
KR970049265A (en) DRAM Refresh Unit in Multi-Master System

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination