KR960024910A - Digital comparison circuit - Google Patents

Digital comparison circuit Download PDF

Info

Publication number
KR960024910A
KR960024910A KR1019940034188A KR19940034188A KR960024910A KR 960024910 A KR960024910 A KR 960024910A KR 1019940034188 A KR1019940034188 A KR 1019940034188A KR 19940034188 A KR19940034188 A KR 19940034188A KR 960024910 A KR960024910 A KR 960024910A
Authority
KR
South Korea
Prior art keywords
output
bits
samples
flag setting
gate
Prior art date
Application number
KR1019940034188A
Other languages
Korean (ko)
Other versions
KR100360871B1 (en
Inventor
김효진
Original Assignee
구자홍
Lg 전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 구자홍, Lg 전자 주식회사 filed Critical 구자홍
Priority to KR1019940034188A priority Critical patent/KR100360871B1/en
Publication of KR960024910A publication Critical patent/KR960024910A/en
Application granted granted Critical
Publication of KR100360871B1 publication Critical patent/KR100360871B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02—Comparing digital values

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

본 발명은 디지탈 비교 회로에 관한 것으로, 종래에는 디지탈 신호 처리(DSP)를 할 때 비교 동작이 많은데 비교 샘플의 수가 증가할수록 연산 시간이 증가하여 시스템의처리 속도가 저하되는 문제점이 있었다. 이러한 문제점을 개선하기 위하여 본 발명은 N개의 샘플을 최상위 비트부터 한 비트씩 서로 비교할 때 "0"값의 비트에 해당하는 샘플을 비교 동작에서 제외시키며 계산 시간이 데이타의 비트 크기에만 외존하도록 하여 비교 연산 시간을 절감시킬 수 있도록 창안한 것으로, 본 발명은 다수의 샘플에서 최대값 또는 최소값을 추출할 때 무효화 되는 비트의 샘플은 비교 동작에서 제외시키므로써 고속의 연산 처리가 가능하고, 전용의 비교기 또는 산술 연산기를 사용할 필요가 없어 간단한 하드웨어로 구현할 수 있으므로 제조 단가를 점갈할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital comparison circuit. In the related art, there are many comparison operations when performing digital signal processing (DSP). However, as the number of comparison samples increases, the computation time increases and the processing speed of the system decreases. In order to solve this problem, the present invention excludes samples corresponding to bits of "0" value from the comparison operation when comparing N samples from the most significant bit to each bit, and compares the calculation time so that only the bit size of the data is independent. In order to reduce the computation time, the present invention allows a high speed computation process by excluding a sample of bits that are invalidated when extracting a maximum or minimum value from a plurality of samples in a comparison operation. There is no need to use an arithmetic operator, so it can be implemented with simple hardware, reducing manufacturing costs.

Description

디지탈 비교 회로.Digital comparison circuit.

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명의 최대값 추출을 위한 신호 흐름도, 제6도는 본 발명의 실행을 위한 실시예의 블럭, 제7도는 제6도에서 각 부의 타이밍도.5 is a signal flow diagram for extracting the maximum value of the present invention, FIG. 6 is a block diagram of an embodiment for implementing the present invention, and FIG. 7 is a timing diagram of each part in FIG.

Claims (5)

대소 비교를 위한 N개의 샘플을 저장하는 레지스터 수단과, 이 레지스터 수단에 저장된 N개의 샘플을 최상위 비트의 위치로 한비트씩 이동시키는 다운 카운팅 수단과, 상기 레지스터 수단에서 출력된 N개의 샘플의 비트가 일치하는지 판별하는 신호 비교수단과, 이 신호 비교 수단에서 비교한 비트가 일치하지 않는다고 판정하면 "0"값을 갖는 해당 샘플을 무효화하여 다음 입력부터는 제외시키는 플래그 설정 수단으로 이루어진 것을 특징으로 하는 디지탈 비교 회로.A register means for storing N samples for large and small comparisons, a down counting means for shifting the N samples stored in the register means by one bit to the position of the most significant bit, and the bits of the N samples output from the register means coincide. A digital comparison circuit comprising: a signal comparing means for discriminating whether or not and a flag setting means for invalidating a sample having a value of "0" and excluding it from the next input when it is determined that the bits compared by the signal comparing means do not match. . 제1항에 있어서, 플래그 설정 수단은 레지스터 수단에서 출력된 N개의 출력을 신호 비교 수단의 출력과 각기 논리 조합하는 N개의 노아게이트와, 클럭(CLK)에 따라 상기 N개의 노아게이트 출력을 각기 홀딩하는 N개의 플립플롭으로 최대값의 샘플을 추출하도록 구성한 것을 특징으로 하는 디지탈 비교 회로.2. The flag setting means according to claim 1, wherein the flag setting means comprises N noar gates for respectively logically combining the N outputs output from the register means with the output of the signal comparing means, and holding the N noar gate outputs according to a clock CLK, respectively. And N flip-flops to extract samples of maximum value. 제2항에 있어서, N개의 플립플롭은 하이를 출력한 경우 그 하이 출력 상태를 계속 유지하는 것을 특징으로 하는 디지탈 비교 회로.3. The digital comparison circuit of claim 2, wherein the N flip-flops continue to maintain their high output state when a high output is output. 제2항에 있어서, N개의 노아게이트를 각각 오아게이트로 대치하여 최소값을 추출하는 것을 특징으로 하는 디지탈 비교 회로.The digital comparison circuit according to claim 2, wherein the minimum values are extracted by replacing the N noah gates with the o gates, respectively. 제1항에 있어서, 신호 비교 수단은 레지스터 수단의 각 출력 비트와 플래그 설정 수단의 각 출력을 논리합하는 N개의 오아게이트 (COR1∼ORn)와 이N개의 오아게이트(OR1~ORn)의 출력을 논리곱하여 모든 비트가 "1"인지 판별하는 앤드게이트(31)와, 상기 레지스터 수단의 각 출력비트와 상기 플래그 설정 수단의 각 출력 비트를 반전시킨 신호를 논리곱하는 N개의 앤드게이트(AN1~ANn)와, 이 N개의 앤드게이트(AN1~ANn)의 출력을 노아링하여 모든 비트가 "0"인지 판별하는 노아게이트(32)와, 상기 앤드게이트(31)와 노아게이ㅌ(32) 출력을 논리합하여 모든 비트가 일치하는지 판정한 신호를 상기 플래그 설정 수단에 입력시키는 오아게이트(33)로 구성한 것을 특징으로 하는 디지탈 비교 회로.The method of claim 1, wherein the signal comparing means is the output of the N Iowa gate (COR 1 ~ORn) and the N Iowa gate (OR 1 ~ ORn) of the respective logical outputs of the output bits of the register means and the flag setting means An AND gate 31 for determining whether all bits are "1" by AND and N number of AND gates (AN 1 to 1 ) for ORing the signal obtained by inverting each output bit of the register means and each output bit of the flag setting means. ANn) and a noar gate 32 for determining whether all the bits are "0" by noarizing the outputs of the N AND gates AN 1 to ANn, and the AND gate 31 and the no-gauge 32. And an orifice (33) for inputting a signal to the flag setting means to determine whether all the bits coincide with the output. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940034188A 1994-12-14 1994-12-14 Digital comparison circuit KR100360871B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940034188A KR100360871B1 (en) 1994-12-14 1994-12-14 Digital comparison circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940034188A KR100360871B1 (en) 1994-12-14 1994-12-14 Digital comparison circuit

Publications (2)

Publication Number Publication Date
KR960024910A true KR960024910A (en) 1996-07-20
KR100360871B1 KR100360871B1 (en) 2003-01-24

Family

ID=37490545

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940034188A KR100360871B1 (en) 1994-12-14 1994-12-14 Digital comparison circuit

Country Status (1)

Country Link
KR (1) KR100360871B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100824378B1 (en) * 2001-06-26 2008-04-22 삼성전자주식회사 Apparatus for comparing bit reverse amplitude of word and method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02165727A (en) * 1988-12-20 1990-06-26 Sanyo Electric Co Ltd Successive comparison type a/d converter and microcomputer having the same
JPH02265326A (en) * 1989-04-05 1990-10-30 Nec Corp Successive comparison type a/d converter
JPH03207114A (en) * 1990-01-09 1991-09-10 Fujitsu Ltd Level identifying circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100824378B1 (en) * 2001-06-26 2008-04-22 삼성전자주식회사 Apparatus for comparing bit reverse amplitude of word and method thereof

Also Published As

Publication number Publication date
KR100360871B1 (en) 2003-01-24

Similar Documents

Publication Publication Date Title
US6219748B1 (en) Method and apparatus for implementing a learn instruction in a content addressable memory device
US7308561B2 (en) Fast, scalable pattern-matching engine
US7596553B2 (en) String matching using data bit masks
KR100288449B1 (en) Condition Detection in Asynchronous Pipelines
US6646899B2 (en) Content addressable memory with power reduction technique
KR960024910A (en) Digital comparison circuit
US8626688B2 (en) Pattern matching device and method using non-deterministic finite automaton
Polig et al. Token-based dictionary pattern matching for text analytics
KR930018871A (en) Methods and circuits for performing running disparity measurements
JPH04350724A (en) Shift extent detecting circuit
Devi et al. Low Energy Asynchronous CAM Based On Reordered Overlapped Search Mechanism
US7221188B2 (en) Logic circuitry
JP2880199B2 (en) Symbol string search method and search device
KR900702450A (en) Parallel String Processor and Method for Minicomputers
JPH0318986A (en) Character recognizing device
Glinski et al. A processor for graph search algorithms
Kumar et al. Fast map-addressing for content addressable memories using register reconfiguration
JPH05113929A (en) Microcomputer
KR900008400B1 (en) Pipeline-typed data classifying apparatus
US5191654A (en) Microprocessor for high speed data processing
JPH0298755A (en) Cache nullification processing system
JPS60142734A (en) Character string comparator
Asynchronous THE INTERNATIONAL JOURNAL OF SCIENCE & TECHNOLEDGE
NV et al. High-Throughput CAM Based On Search and Shift Mechanism
KR0147707B1 (en) Zero bit string detection circuit

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
N231 Notification of change of applicant
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070918

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee