KR960020895A - X-decoder circuit of semiconductor memory device - Google Patents

X-decoder circuit of semiconductor memory device Download PDF

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Publication number
KR960020895A
KR960020895A KR1019940039242A KR19940039242A KR960020895A KR 960020895 A KR960020895 A KR 960020895A KR 1019940039242 A KR1019940039242 A KR 1019940039242A KR 19940039242 A KR19940039242 A KR 19940039242A KR 960020895 A KR960020895 A KR 960020895A
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KR
South Korea
Prior art keywords
node
gate
vss
nmos transistor
potential
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KR1019940039242A
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Korean (ko)
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KR100316180B1 (en
Inventor
김정필
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019940039242A priority Critical patent/KR100316180B1/en
Publication of KR960020895A publication Critical patent/KR960020895A/en
Application granted granted Critical
Publication of KR100316180B1 publication Critical patent/KR100316180B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)

Abstract

본 발명은 반도체 기억소자의 X-디코더 회로에 관한 것으로, X-디코더 프리차지 신호(Xdpb)를 Vpp전위로 사용해야 하는 단점을 극복하기 위해서 Vpp전위 쉬프트(shifter)를 구현함으로써, Vpp전위의 로딩(loading) 감소로 Vpp발전기의 면적을 줄일뿐 아니라, 전류소모를 줄이는 효과가 있다.The present invention relates to an X-decoder circuit of a semiconductor memory device, and implements a Vpp potential shifter to overcome the disadvantage of using the X-decoder precharge signal Xdpb as the Vpp potential. Reducing loading not only reduces the area of the Vpp generator, but also reduces the current consumption.

Description

반도체 기억소자의 X-디코더회로X-decoder circuit of semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제5도는 본 발명의 제1실시예에 따른 X-디코더 회로도,5 is an X-decoder circuit diagram according to a first embodiment of the present invention;

제7도는 본 발명의 제2실시예에 따른 X-디코더 회로의 Vpp전위 쉬프트의 회로도.7 is a circuit diagram of the Vpp potential shift of the X-decoder circuit according to the second embodiment of the present invention.

Claims (2)

반도체 메모리 소자의 엑스 디코더 회로에 있어서, Vpp전위 및 노드(N13, N14) 사이에 크로스 커플(cross-coupled)구조로 접속된 PMOS트랜지스터(Q17, Q18)와, 상기 노드(N13) 및 접지전압(Vss) 사이에 접속되며 게이트에 X-디코더 프리차지 신호(Xpd)가 인가되는 NMOS트랜지스터(Q19)와, 상기 노드(N13) 및 전지전압(Vss)사이에 접속되며 게이트에 상기 노드(N14)가 연결된 NMOS트랜지스터(Q20)로 구성된 상기 Vpp전위 쉬프트부와, 상기 노드(N14) 및 접지전압(Vss) 사이에 직렬접속되며 게이트에 각각 어드레스 디코딩된 로우 어드레스 조합신호가 인가되는 NMOS트랜지스터 (Q21∼Q23)로 구성된 상기 어드레스 디코딩부와, px<0>신호 및 노드(N17) 사이에 접속되며 게이트가 상기 노드(N14)에 연결된 PMOS트랜지스터(Q24)와, 상기 노드(N17) 및 접지전압(Vss) 사이에 접속되며 게이트에 제어신호(/AX01<0>)가 인가되는 NMOS트랜지스터(Q26)와, 워드라인 구동신호(WL<0>)를 출력하는 상기 노드(N17)로 구성된 상기 드라이버부를 구비하는 것을 특징으로 하는 X-디코더 회로.In the X decoder circuit of a semiconductor memory device, PMOS transistors Q17 and Q18 connected in a cross-coupled structure between the Vpp potential and the nodes N13 and N14, and the node N13 and the ground voltage ( Is connected between the NMOS transistor Q19 and the node N13 and the battery voltage Vss, which are connected between Vss and to which an X-decoder precharge signal Xpd is applied to a gate, and the node N14 is connected to a gate. NMOS transistors Q21 to Q23 connected in series between the Vpp potential shift unit including the connected NMOS transistor Q20 and the node N14 and the ground voltage Vss, and to which a row address combination signal decoded to a gate is applied, respectively. A PMOS transistor (Q24) connected between the address decoding unit (Px) and a node (N17), the gate of which is connected to the node (N14), the node (N17), and the ground voltage (Vss). Connected between the gate and the control signal (/ AX01) And the driver section comprising an NMOS transistor (Q26) to which <0>) is applied and the node (N17) for outputting a word line driving signal (WL <0>). 제1항에 있어서, 상기 Vpp전위 쉬프트부는, Vpp전위 및 노드(N18, N19) 사이에 크로스 커플로 접속된 PMOS트랜지스터 (Q27, Q28)와, 상기 노드(N18) 및 접지전위(Vss) 사이에 접속되며 게이트에 상기 노드(N14 : ⓐ)가 연결된 NMOS트랜지스터(Q29)와, 상기 노드(N19) 및 접지전위(Vss) 사이에 접속되며 게이트에 상기 노드(N13 : ⓑ)가 연결된 NMOS트랜지스터 (Q30)와, 상기 노드(N19)의 전위를 출력하는 출력단자(out)로 구성된 것을 특징으로 하는 X-디코더 회로.2. The Vpp potential shift unit according to claim 1, wherein the Vpp potential shift unit is connected between the PMOS transistors Q27 and Q28 connected in cross-couple between the Vpp potential and the nodes N18 and N19, and between the node N18 and the ground potential Vss. NMOS transistor Q29 connected to a node N14 (ⓐ) connected to a gate, and an NMOS transistor Q30 connected between the node N19 and ground potential Vss and connected to a gate N13 (ⓑ) at a gate thereof. ) And an output terminal (out) for outputting the potential of the node (N19). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940039242A 1994-12-30 1994-12-30 X-decoder circuit of semiconductor memory device KR100316180B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940039242A KR100316180B1 (en) 1994-12-30 1994-12-30 X-decoder circuit of semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940039242A KR100316180B1 (en) 1994-12-30 1994-12-30 X-decoder circuit of semiconductor memory device

Publications (2)

Publication Number Publication Date
KR960020895A true KR960020895A (en) 1996-07-18
KR100316180B1 KR100316180B1 (en) 2002-04-24

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Publication number Priority date Publication date Assignee Title
KR102302591B1 (en) 2015-09-22 2021-09-15 삼성전자주식회사 Row Decoder with reduced size and Memory Device having the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950003389Y1 (en) * 1992-04-16 1995-04-27 문정환 Word-line driving circuit of dram

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