KR960019705A - Twin well formation method of semiconductor device - Google Patents

Twin well formation method of semiconductor device Download PDF

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Publication number
KR960019705A
KR960019705A KR1019940030523A KR19940030523A KR960019705A KR 960019705 A KR960019705 A KR 960019705A KR 1019940030523 A KR1019940030523 A KR 1019940030523A KR 19940030523 A KR19940030523 A KR 19940030523A KR 960019705 A KR960019705 A KR 960019705A
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South Korea
Prior art keywords
well
forming
wells
semiconductor device
silicon oxide
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KR1019940030523A
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Korean (ko)
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KR0137823B1 (en
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황준
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김주용
현대전자산업 주식회사
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Publication of KR960019705A publication Critical patent/KR960019705A/en
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Publication of KR0137823B1 publication Critical patent/KR0137823B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체 소자의, 래치 업(latch-up) 방지 및 웰의 자기 정렬을 위한 트윈 웰 형성 방법에 관한 것이다. 본 발명은 마스크 패턴에 의한 실리콘 기판 웰 내부에 직접적인 이온 주입 공정 없이, n웰 및 p웰을 형성할 영역의 웨이퍼 기판 실리콘을 선택적 에피택셜 성장법으로 각각 개별적으로 성장시키면서 동시에 성장되는 각각의 n웰 및 p웰 영역에 각각 대응하는 p형 도펀트 함유 가스 및 p형 도펀트 함유 가스를 주입하여, 기판의 상부로 돌출되는 트윈 웰을 형성함으로써, 래치 업을 방지하고, 자기 정렬이 가능하며, 종래보다 고집적 회로 설계에 유리하고, 제조공정시간을 단축하는 등의 효과가 있다.The present invention relates to a method of forming a twin well for preventing latch-up and self-alignment of a semiconductor device. According to the present invention, each of the n wells grown at the same time while growing the wafer substrate silicon in the region where n wells and p wells are to be formed individually by a selective epitaxial growth method without a direct ion implantation process inside a silicon substrate well by a mask pattern And a p-type dopant-containing gas and a p-type dopant-containing gas corresponding to the p-well region, respectively, to form a twin well that protrudes to the upper portion of the substrate, thereby preventing latch-up and allowing self-alignment. It is advantageous for circuit design and has an effect of shortening the manufacturing process time.

Description

반도체 소자의 트윈 웰 형성방법Twin well formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제5도 내지 제9도는 본 발명에 따른 반도체의 트윈 웰 형성 방법을 보인 공정도.5 to 9 are process charts showing a twin well forming method of a semiconductor according to the present invention.

Claims (7)

반도체 소자의 트윈 웰 형성방법에 있어서, n웰 및 p웰을 형성할 영역의 웨이퍼 기판 실리콘을 선택적 에피택셜 성장법으로 각각 개별적으로 성장시키면서 동시에 성장되는 각각의 n웰 및 p웰 영역에 각각 대응하는 n형 도펀트 함유 가스 및 p형 도펀트 함유 가스를 주입하여 트윈 웰을 형성하는 것을 특징으로 하는 반도체 소자의 트윈 웰 형성방법.In the method of forming a twin well of a semiconductor device, the wafer substrate silicon in the region where n and p wells are to be formed is individually grown by selective epitaxial growth, respectively, and corresponding to each of the n well and p well regions that are simultaneously grown. A twin well forming method of a semiconductor device, characterized by forming a twin well by injecting an n-type dopant-containing gas and a p-type dopant-containing gas. 제1항에 있어서, 웰을 형성할 영역에 실리콘 산화막을 형성하는 단계, n웰 및 p웰 중 어느 하나의 웰을 우선적으로 형성하기 위하여 상기 나의 웰을 형성한 영역 상부의 실리콘 산화막을 식각하는 단계, 상기 실리콘 산화막이 식각된 부분의 실리콘을 선택적으로 에피택셜 성장시키면서, 동시에 상기 하나의 웰을 형성하는데 필요한 도펀트 함유 가스를 주입하는 단계와 또 다시 실리콘 산화막을 전면에 성장시키는 단계와 상기 다른 하나의 웰을 형성하는 영역 상부의 실리콘 산화막을 식각하는 단계, 상기 실리콘 산화막이 식각된 부분의 실리콘을 선택적으로 에피택셜 성장시키면서, 동시에 상기 다른 하나의 웰을 형성하는데 필요한 도펀트 함유 가스를 주입하고, 불필요한 여분의 실리콘 산화막을 제거하는 단계로 이루어지는 반도체 소자의 트윈 웰 형성방법.The method of claim 1, further comprising: forming a silicon oxide film in a region where the wells are to be formed, and etching a silicon oxide layer on the region where the wells are formed to preferentially form any one of n wells and p wells. Selectively injecting a dopant-containing gas required to form the one well while selectively epitaxially growing silicon in the portion where the silicon oxide film is etched, and further growing the silicon oxide film on the front surface and the other Etching the silicon oxide film over the region forming the well, while selectively epitaxially growing silicon in the portion where the silicon oxide film is etched, simultaneously injecting a dopant-containing gas necessary to form the other well, and unnecessary extra A twin well of a semiconductor device comprising the step of removing a silicon oxide film St. ways. 제2항에 있어서, n웰을 형성하는데 필요한 도펀트 함유 가스는 PH3가스이고, p웰을 형성하는데 필요한 도펀트 함유 가스는 B2H6가스인 것을 특징으로 하는 반도체 소자의 트윈 웰 형성방법.The method of claim 2, wherein the dopant-containing gas required for forming the n well is a PH 3 gas, and the dopant-containing gas required for forming the p well is a B 2 H 6 gas. 제2항에 있어서, n웰과 p웰의 중간부에 웰의 자기 정렬을 위한 실리콘 산화막이 공정의 부산물로서 형성되는 것을 특징으로 하는 반도체 소자의 트윈 웰 형성방법.3. The method of forming a twin well of a semiconductor device according to claim 2, wherein a silicon oxide film for self-alignment of the well is formed in the middle of the n well and the p well as a by-product of the process. 제2항에 있어서, 성장되는 n웰 및 p웰의 실리콘 두께는 래치 업이 일러나지 않는 정도의 두께인 것을 특징으로 하는 반도체 소자의 트윈 웰 형성방법.3. The method of forming a twin well of a semiconductor device according to claim 2, wherein the silicon thickness of the n well and p well to be grown is such that the latch up is unknown. 제5항에 있어서, 상기 성장 실리콘의 두께는 3㎛ 정도인 것을 특징으로 하는 반도체 소자의 트윈 웰 형성방법.The method of claim 5, wherein the growth silicon has a thickness of about 3 μm. 제1항에 있어서, n웰 및 p웰은 웨이퍼 기판위에 돌출되도록 형성되는 것을 특징으로 하는 반도체 소자의 트윈 웰 형성방법.The method of claim 1, wherein the n well and p well are formed to protrude on the wafer substrate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940030523A 1994-11-19 1994-11-19 Manufacturing method of twin well KR0137823B1 (en)

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KR960019705A true KR960019705A (en) 1996-06-17
KR0137823B1 KR0137823B1 (en) 1998-04-28

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