KR960018865A - Multivalued logic negation unit - Google Patents

Multivalued logic negation unit Download PDF

Info

Publication number
KR960018865A
KR960018865A KR1019940029919A KR19940029919A KR960018865A KR 960018865 A KR960018865 A KR 960018865A KR 1019940029919 A KR1019940029919 A KR 1019940029919A KR 19940029919 A KR19940029919 A KR 19940029919A KR 960018865 A KR960018865 A KR 960018865A
Authority
KR
South Korea
Prior art keywords
binary
input
multivalued
negation
logic
Prior art date
Application number
KR1019940029919A
Other languages
Korean (ko)
Other versions
KR0138856B1 (en
Inventor
김진업
김선영
Original Assignee
양승택
재단법인 한국전자통신연구소
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 양승택, 재단법인 한국전자통신연구소 filed Critical 양승택
Priority to KR1019940029919A priority Critical patent/KR0138856B1/en
Publication of KR960018865A publication Critical patent/KR960018865A/en
Application granted granted Critical
Publication of KR0138856B1 publication Critical patent/KR0138856B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/49—Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix non-linear PCM

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)

Abstract

본 발명은 다치 논리 값의 부정(NOT)을 구하는 다치 논리 부정 연산장치에 관한 것으로, 각각 소정 비트를 갖는 k+1(k는 임의의 양의 정수)개의 이진수(S0-Sk) 입력을 한 개씩 받아 들여 이진 논리 부정 연산을 수행하는 k+1개의 이진 논리 부정 연산기와, 이 논리 부정 연산기들의 출력을 받아 들여 덧셈하는 산술 덧셈기로 구성되어서, 경제적인 다치 논리회로의 설계가 가능하게 된다.The present invention relates to a multi-valued logical negation device for finding a NOT value of a multi-valued logical value. The present invention relates to k + 1 (k is an arbitrary positive integer) input of binary numbers (S 0 -S k ) each having a predetermined bit. K + 1 binary logic negation operators that accept binary logic negation operations one by one and an arithmetic adder that accepts and adds the outputs of these logic negation operations enable economic design of multivalued logic circuits.

Description

다치 논리 부정 연산장치Multivalued logic negation unit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 본 발명에 따른 다치 논리 부정 연산장치.4 is a multivalued logical negation apparatus according to the present invention.

Claims (3)

최대치 A(여기서, A는 임의의 양의 정수)를 갖는 다치 논리 입력(X)의 다치 논리 부정 연산을 수행하는 장치에 있어서, 상기 다치 논리 입력(X)을 받아 들이는 제1의 입력단자와, 상기 다치 논리 입력(X)의 상기 최대치(A)를 받아 들이는 제2의 입력단자와, 하나의 출력단자를 구비하는 뺄셈기를 포함하는 것을 특징으로 하는 다치 논리 부정 연산장치.A device for performing a multivalued logic negation operation of a multivalued logic input (X) having a maximum value A (where A is any positive integer), comprising: a first input terminal that accepts the multivalued logic input (X); And a subtractor having a second input terminal for receiving the maximum value A of the multivalued logic input (X) and a single output terminal. 각각 소정 비트를 갖는 k+1(여기서, k는 임의의 양의 정수)개의 이진수(S0∼Sk) 입력의 다치 논리 부정 연산을 수행하는 장치에 있어서, 상기 이진수 입력은 한 개씩 받아 들여 이진 논리 부정 연산을 수행하는 k+1개의 이진 논리 부정 연산기와, 상기 이진 논리 부정 연산기들의 출력을 받아 들여 덧셈하는 산술 덧셈기를 포함하는 것을 특징으로 하는 다치 논리 부정 연산장치.In the apparatus for performing multi-valued logical negation of k + 1 binary (S 0 -S k ) inputs each having a predetermined bit, wherein the binary input is one binary input. And k + 1 binary logic negation operators for performing logical negation operations, and an arithmetic adder for receiving and adding outputs of the binary logic negation operators. 각각 소정 비트용 갖는 k+1(여기서, k는 임의의 양의 정수)개의 이진수(S0∼Sk) 입력의 다치 논리 부정 연산을 수행하는 장치에 있어서; 상기 이진수 입력들의 각 비트별로 순차로 받아 들여 덧셈하는 것에 의해 상기 이진수 입력에 해당하는 다치 논리값을 구하는 산술 덧셈기와; 상기 덧셈기의 다치 논리값(X)을 받아 들이는 제1의 입력 단자와, 상기 다치 논리 입력(X)의 최대치(A)를 받아 들이는 제2의 입력단자와, 하나의 출력단자를 구비하는 뺄셈기를 포함하는 것을 특징으로 하는 다치 논리 부정 연산장치.An apparatus for performing a multivalued logical negation operation of k + 1 binary (S 0 to S k ) inputs each having a predetermined bit, wherein k is any positive integer; An arithmetic adder for obtaining a multi-valued logical value corresponding to the binary input by sequentially receiving and adding each bit of the binary inputs; A first input terminal that accepts the multivalued logic value X of the adder, a second input terminal that receives the maximum value A of the multivalued logic input X, and one output terminal; A multivalued logical negation device comprising a subtractor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940029919A 1994-11-15 1994-11-15 Multi-nary not logic device KR0138856B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940029919A KR0138856B1 (en) 1994-11-15 1994-11-15 Multi-nary not logic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940029919A KR0138856B1 (en) 1994-11-15 1994-11-15 Multi-nary not logic device

Publications (2)

Publication Number Publication Date
KR960018865A true KR960018865A (en) 1996-06-17
KR0138856B1 KR0138856B1 (en) 1998-06-15

Family

ID=19397935

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940029919A KR0138856B1 (en) 1994-11-15 1994-11-15 Multi-nary not logic device

Country Status (1)

Country Link
KR (1) KR0138856B1 (en)

Also Published As

Publication number Publication date
KR0138856B1 (en) 1998-06-15

Similar Documents

Publication Publication Date Title
US3767906A (en) Multifunction full adder
KR970060485A (en) I / O device
KR960018870A (en) Multivalued logical product
KR960018871A (en) Multi-valued OR
KR930006539A (en) adder
US3566098A (en) High speed adder circuit
KR960018865A (en) Multivalued logic negation unit
US6003059A (en) Carry select adder using two level selectors
US5777918A (en) Fast multiple operands adder/subtracter based on shifting
KR970703559A (en) ALTERNATING POLARITY CARRY LOOK AHEAD ADDER CIRCUIT
KR960018883A (en) Multivalued exclusive OR operation unit
KR100306108B1 (en) Digit Rounding Prediction Circuit
KR950015063A (en) Exclusive logical OR operator and method of multivalued logic and binary logic
US3423577A (en) Full adder stage utilizing dual-threshold logic
RU2043651C1 (en) Adder
KR950009684B1 (en) Full adder
KR20000050721A (en) Layered orthogonal code generation apparatus and method
US7028069B1 (en) Dynamic circuit using exclusive states
Moraga Design of a modulo p multiplier
KR0143710B1 (en) Propagation three inputs adder
KR100201030B1 (en) Select encoder network
KR970005599B1 (en) A circuit for getting digital correlation values
KR100226757B1 (en) Parallel divider
KR960001978A (en) Barrel shifter circuit
KR970022730A (en) High speed addition circuit

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080214

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee