KR960012748A - Low Noise Amplifier Circuit for Digital Cellular - Google Patents

Abstract

1. the technical field to which the invention described in the claims belongs; An amplifier circuit of a mobile communication system.

2. The technical problem to be solved by the invention; Provides a high power amplifier circuit.

3. Summary of the solution of the invention; An input matching and microstrip line for input matching and choking an applied high frequency signal, a transistor having an emitter ground to low noise amplify the signal matched and choked by the input matching and microstripline, and First, second, and third amplifiers each having an output match and a micro strip line for output matching and choking the signal amplified by the first signal; Active biasing means including first, second and third bias circuits for providing the necessary bias voltages through the first, second and third microstrip lines in the first, second and third amplifiers, respectively; And a power supply means for providing a stable power source to the biasing means.

4. Significant use of the invention; Used for low noise amplification of base stations for digital cellular.

Description

Low Noise Amplifier Circuit for Digital Cellular

As this is a public information case, the full text was not included.

1 is a block diagram of a low noise amplifier circuit of the present invention.

2 is a concrete circuit diagram according to FIG.

Claims (5)

An amplifier circuit suitable for a digital cellular system, comprising: a first input match and micro strip line for input resistance and choking an applied high frequency signal and a low noise matched and choked by the first input match and micro strip line A first amplifier having a first transistor having an emitter ground for amplifying, and a first output and micro strip line for output matching and choking the signal amplified by the first transistor; An emitter for low noise amplifying a second input match and microstripline for input matching and choking the signal applied from the first amplifier and the signal matched and choked by the second input match and microstrip line A second amplifier having a second transistor having a ground, a second output match and a micro strip line for output matching and choking the signal amplified by the second transistor; An emitter ground to low noise amplify the third input matched and microstrip line for input matching and choking the signal applied from the second amplifier and the matched choked signal by the third input matched and microstrip line A third amplifier having a third transistor having a third output matching and a micro strip line for output matching and choking the signal amplified by the third transistor; First, second and third biases for providing first, second and third bias voltages for providing the necessary bias voltages through the first, second and third microstrip lines in the first, second and third amplifiers, respectively Active biasing means comprising a circuit; And power supply means for providing stable power to the biasing means. The circuit of claim 1, wherein a frequency of the high frequency signal applied to the first amplifier has a frequency band of 820 MHz to 850 MHz. The circuit of claim 1, wherein the total gain of the first, second and third amplifiers is 40 dB or more, the three-stage intercept point is +35 dBm or more, and each has a noise figure of 1.6 dB or less. The circuit of claim 1, wherein the first, second and third transistors are microwave transistors of PNP type. 2. The circuit of claim 1 wherein each microstrip line is about 0.25 mm thick and about 58.52 mm long. ※ Note: It is to be disclosed based on the initial application.