KR960012643B1 - Method for forming the element isolation film of the semiconductor element - Google Patents

Abstract

The method of manufacturing isolation film of semiconductor device comprises the steps of : stacking a pad oxide film(2), a polycrystal silicone(3) and a silicone nitrided film(4) on a silicon substrate(1); forming a narrow groove(5) and a wide groove(6) by etching the polycrystal silicone(3) after etching the silicone nitrided film(4) of the exposed region; and forming a narrow and a wide isolation oxide film(7,8) by oxidizing the polycrystal silicone(3) and the silicone substrate(1) below the grooves(5,6), and removing the silicone nitrided film(4), the polycrystal silicone(3) and the pad oxide film(2).

Description

Device Separation Method of Semiconductor Device

1 to 3 are cross-sectional views showing a device isolation film manufacturing process of a semiconductor device according to an embodiment of the prior art.

4A to 4D are cross-sectional views showing a device isolation film manufacturing process of a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1, 11: silicon substrate, 2, 12: pad oxide film,

3, 13 polycrystalline silicon, 4, 14 silicon nitride film,

5, 15: narrow groove, 6, 16: wide groove,

7, 8, 17, 18: device isolation oxide film.

The present invention relates to a method for manufacturing a device isolation film of a semiconductor device, and as the degree of integration of semiconductor devices increases, the width of the device isolation film becomes narrower, so that the growth thicknesses of the narrow width of the device isolation film and the oxide of the wide couple are different. . Therefore, when removing from the upper layer to the polysilicon using a device isolation film forming mask in the PBI (poly buffered LOCOS (PBL) structure), the etching thickness difference in the narrow and wide polycrystalline silicon After the removal, the oxide film is grown to increase the reliability of the device by preventing the device isolation film from thinning at a narrow device isolation region by increasing the thickness of the two device isolation films.

In order to increase the integration of devices in terms of high integration, it is necessary to reduce the dimension of each device and to reduce the area of the width and area of the isolation region existing between the devices. The device isolation technique is a technique for determining the memory cell size in that the size of the cell determines the size of the cell.

Conventional techniques for manufacturing device isolation films include the LOCOS (LOCOS: LOCOS) method, the PBL method in which an oxide film, a polycrystalline silicon layer, and a nitride film are laminated on a silicon substrate, and grooves are formed in the substrate. Afterwards, there is a trench method for embedding with an insulating material.

In the case of using the above-mentioned PBL, buzz big is generated by side diffusion of oxygen during field oxidation. Particularly, when the density is high, the device isolation region may have a smaller width and a smaller thickness of the oxide film, so that the reliability of the device isolation region may be weaker than that of other methods.

An embodiment of a device isolation film manufacturing method of a semiconductor device according to the prior art will be described in detail with reference to FIGS. 1 to 3.

FIG. 1 is a cross-sectional view illustrating a PBL structure formed by sequentially stacking a pad oxide film 12, a polycrystalline silicon 13, and a silicon nitride film 14 on the silicon substrate 11. FIG.

2 shows that a small groove 15 and a wide groove 16 are formed by etching the silicon nitride film 14 and the polycrystalline silicon 13 in an exposed region by using a mask for forming an isolation layer in the PBL structure. It is sectional drawing.

3 is a cross-sectional view illustrating the formation of device isolation oxide films 17 and 18 on the silicon substrate 11 at the bottom of the grooves 15 and 16 by a thermal oxidation process. Although the device isolation oxide film 17 formed in the groove 15 has a small thickness, the silicon substrate 11 in the lower portion cannot be oxidized due to the stress of the device isolation oxide film 17, but the thickness is thin. The formed device isolation oxide film 18 is sufficiently wide so that the lower silicon substrate 11 is thickly oxidized to form a large device isolation oxide film 18. As a result, a step is generated between the device isolation oxide layers 17 and 18.

As described above, a step is formed between the device isolation oxide layers formed on the silicon substrate, and the etching rate is large when etching to form a contact, so that the etching process is difficult. Due to problems such as short between word line or bit line and charge storage electrode, short circuit of line due to step difference or increase of resistance, actual process margin is very small.

Therefore, in order to solve the above problem, the device isolation oxide film is formed by an oxidation process in a state where the thickness of the polycrystalline silicon remaining on the upper portion of the pad oxide film in which the small device isolation film and the wide device isolation film are formed is different. An object of the present invention is to fabricate a device isolation film such that the thickness of the device isolation oxide film is small and wide.

In the present invention, the polysilicon has a thicker thickness of the polysilicon in a place where a small device isolation oxide film is formed by using a point in which the polysilicon is faster than the single crystal silicon (silicon substrate), and the polycrystalline silicon is formed in a wide device isolation oxide film. The thickness of the silicon is left thin so that the oxidation rate is similar during the oxidation process.

A feature of the present invention for achieving the above object is a process of laminating a pad oxide film, a polysilicon film and a silicon nitride film on top of a silicon substrate, and etching a silicon nitride film in an exposed region by using a mask for forming a small device isolation film. After that, the small thickness of the polysilicon of the etched portion is etched to form a narrow groove, and the silicon nitride film of the exposed region is etched by using a wide element isolation film forming mask, and then the polysilicon underneath Etching a large thickness to form a wide groove, and oxidizing the polycrystalline silicon and the silicon substrate under the groove to form a small and wide device isolation oxide film together, and then remaining silicon nitride film, polycrystalline silicon, It includes a step of removing the pad oxide film.

Hereinafter, a device isolation film manufacturing method of a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.

4A to 4D are sectional views showing the process steps of manufacturing the device isolation film according to the present invention.

FIG. 4A is a cross-sectional view showing that the pad oxide film 2, the polycrystalline silicon 3, and the silicon nitride film 4 are stacked and formed on the silicon substrate 1 in a PBL structure.

4B shows a predetermined thickness (total thickness) of the silicon nitride film 4 and the polycrystalline silicon 3 underneath, for example, using a device isolation film forming mask (not shown) to form a small device isolation film in a cell region. Is about 20-40%) to form a narrow groove (5). Here, if the predetermined thickness of the polysilicon 3 is left, less side diffusion occurs at the initial stage of oxidation when the device isolation film is formed, so that the growth of the Buzzvik occurs less, and the device isolation film grows faster.

4C shows, for example, the silicon nitride film 4 and the polysilicon 3 underneath the polysilicon 3 underneath by using a device isolation film forming mask to form a wide device isolation film in the peripheral circuit area. It is sectional drawing which formed the groove | channel 6 of wide width by etching thickness (about 70-90% of total thickness). For reference, the wide groove 6 may be formed before the narrow groove 5.

In FIG. 4D, silicon oxides 7 and 8 formed on the polycrystalline silicon 3 and the silicon substrate 1 under the narrow grooves 5 and the wide grooves 6 are formed by the oxidation process, respectively. It is sectional drawing which shows the removal of the nitride film 4, the polycrystalline silicon 3, and the pad oxide film 2. Here, the device isolation oxide film 7 formed in the narrow grooves 5 is rapidly grown by the remaining polycrystalline silicon 3, and the device isolation oxide film 8 formed in the wide grooves 6 is a silicon substrate. Growth in polycrystalline silicon is relatively slower than in polycrystalline silicon. Therefore, the thicknesses of the device isolation films formed in the wide grooves and the narrow grooves are almost similar.

As described above, according to the present invention, the thicknesses of the small device isolation oxide film and the wide device isolation oxide film are almost the same, thereby facilitating the subsequent process, and increasing the degree of integration by suppressing the growth of the buzz big.

Claims (4)

In the method of manufacturing a device isolation film of a semiconductor device, a step of laminating a pad oxide film, a polysilicon film and a silicon nitride film on a silicon substrate, and using a small mask for forming a device isolation film, and then cutting the silicon nitride film in the exposed area And etching the polysilicon underneath to form a narrow groove, and etching the silicon nitride film in the exposed area by using a mask formed with a wide element isolation film, and then etching the polysilicon underneath to form the wide groove. And forming a small and wide device isolation oxide film by oxidizing the polycrystalline silicon and the silicon substrate under the groove by an oxidation process, and then removing the remaining silicon nitride film, polycrystalline silicon, and pad oxide film. Device isolation film manufacturing method of a semiconductor device, characterized in that. The method of claim 1, wherein a wide groove is formed first and a small groove is formed in the process. The method of claim 1, wherein, when the narrow grooves are formed, polysilicon is etched from 20 to 40% of the total thickness of the polysilicon. The method of claim 1, wherein the polysilicon is etched at 70-90% of the total thickness of the polysilicon when the wide groove is formed.