KR960012600B1 - Clamp compensation circuit in a color difference signal - Google Patents

Abstract

The circuit includes a low pass filter(1) for dividing color subcarrior, a decoding integrated element(2) for dividing color signal into color difference signal, a clamp circuit unit(3) for adjusting color difference signal to DC level by using memory controller(6), a multiplexer(4) for selecting and generating color difference signal continuously, an analogy/digital converter(5) for transferring output signal to digital signal and generating it, a memory controller(6) for performing reduction and magnification of image signal, a data level discriminating logic unit(11), a try state buffer(12), and limiter/integrator(13).

Description

Clamp Correction Circuit of Color Difference Signal

1 is a block diagram showing a conventional color difference signal clamp process.

2 is a color difference signal clamp correction block diagram of the present invention.

3 is a detailed circuit diagram of the data level discrimination logic of FIG.

4 is a detailed circuit diagram of the limiter and integrator of FIG.

* Explanation of symbols for main parts of the drawings

1: low pass filter 2: decoding integrated device

3: clamp circuit part 4: multiplexer

5: analog / digital converter 6: memory controller

11: data level discrimination logic section 12: tri-state buffer

13: limiter and integrator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clamp correction circuit of a color difference signal, and more particularly, to demodulate a color difference signal in a processing for reducing or expanding a video signal of a television or video cassette recorder, and to digitally convert the demodulated color difference signal. The present invention relates to a clamp correction circuit for a color difference signal, which makes it possible to compensate for color distortion caused by the clamp level variation.

In the conventional color difference signal clamp circuit, as shown in FIG. 1, a low pass filter 1 for separating color subcarriers from an image signal VS and a color signal output from the low pass filter 1 have two color differences. The decoding integrated device 2 separating the signals BY and RY and the color difference signals BY and RY output from the decoding integrated device 2 are clamp pulse signals CP from the memory controller 6. Is outputted by sequentially selecting the clamp circuit section 3 matching the DC level and the color difference signals BY and RY output from the clamp circuit section 3 by the selection control signal of the memory controller 6. A multiplexer (4), an analog / digital converter (5) for converting and outputting a signal selected by the multiplexer (4) and outputting the digital signal, and the output signal of the analog / digital converter (5) Consists of a memory controller 6 for reducing and enlarging video signals As a result, the DC level of the clamp circuit section 3 can be set by adjusting the variable resistor VR ₁ .

In other words, the direct current level was adjusted by the variable resistor VR ₁ so that the two color difference signals BY and RY were positioned between the reference voltage high and low of the analog / digital converter 5. Therefore, the DC level of the two color difference signals BY (RY) changes due to the shaking of the reference color subcarrier of the decoding integrated device 2, and the data changes when the reference voltage of the analog / digital converter 5 changes. In this case, the color phase is distorted during color digital encoding.

Further, even if the DC level of the clamp circuit section 3 is adjusted by the variable resistor VR ₁ , the DC level changes as the power supply of the power supply terminal B ⁺ changes. Meanwhile, when the clamp pulse signal CP is output from the memory controller 6, the clamp circuit unit 3 samples a DC level of the color difference signal BY RY and maintains the DC level constant for one horizontal synchronization. .

As described above, in the conventional apparatus, since the DC level of two color difference signals is changed, color shift occurs during color digital signal encoding, and the reference voltage of the analog / digital converter is affected by changes in temperature characteristics and power supply. As a result of this change, the analog / digital conversion value is distorted, which has a drawback in the color distorted phenomenon in color digital signal encoding.

In order to solve the above-mentioned drawback, the present invention detects the DC level change amount of the clamp circuit part from the digital signal converted by the analog / digital converter and input to the memory controller, and compensates the DC level of the clamp circuit part according to the detected signal. Invented to prevent the distortion of the color in advance, it will be described in detail with reference to the accompanying drawings as follows.

2 is a block diagram of the color difference signal clamp correction of the present invention, as shown therein, a low pass filter 1 for separating color subcarriers from an image signal VS, and a color signal output from the low pass filter 1; The decoding integrated element 2 separating the two color difference signals BY and RY, and the color difference signals BY and RY output from the decoding integrated element 2 are clamp pulses from the memory controller 6. When the signal CP is outputted, the clamp circuit 3 matching the DC level and the color difference signals BY and RY output from the clamp circuit 3 are sequentially arranged by the selection control signal of the memory controller 6. Multiplexer 4 for selecting and outputting the signal, an analog / digital converter 5 for converting and outputting a signal selected and outputted in the multiplexer 4 into a digital signal, and an output signal of the analog / digital converter 5 Memo to reduce or enlarge video signal In a circuit composed of a controller (6), in accordance with a data level discrimination logic unit (11) for discriminating the level of digital data input to the memory controller (6) and a discrimination signal from the data level discrimination logic unit (11). A predetermined level of DC voltage is applied to the clamp circuit section 3 in accordance with the tri-state buffer 12 which is in a high impedance state or outputs a high potential and a low potential signal and the output signal state of the tri-state buffer 12. It consists of a limiter and an integrator (13).

And a third NOR gate turn via an inverter (I ₁₎ a, the data determination bit signal terminals (B ₆₎ as the second one even this shown as a detailed circuit diagram of the hollow weave portion 11 is part of data level determination (NOR ₁₎ The common terminal is connected to the input terminal of the one side input terminal and the second state tri-state buffer 12, and the data discrimination bit signal terminals B ₅ to B ₁ are connected to the other input terminal of the NOR gate NOR ₁ . the NOR gate (NOR ₁₎ the output terminal and an enable mode, the signal terminal (S _1), an analog / digital clamp pulse signal terminals (S _2), the color signal selection mode, the signal terminal (S ₃₎ NOR gate (NOR ₂₎ And an output terminal of the NOR gate NOR ₂ connected to a control terminal of the tri-state buffer 12.

FIG. 4 is a detailed circuit diagram of the limiter and integrator 13 of FIG. 2. As shown in FIG. 4, the analog / digital reference high voltage terminal V _rh and the analog / digital reference low voltage terminal V _r1 are resistors R. ₁₁ ), (R ₁₂ ) are connected in common, and the connection point is connected to the resistor (R ₁₅ ) and the capacitor (C ₁₁ ) through parallel connected resistors (R ₁₃ ) and diodes (D ₁₁ ) and (D ₁₂ ). and the third also the resistance (R ₁₅₎ and capacitor (C _11), the second FIG clamp circuit the junction box and addition, the connection point to the connection point of the through an output terminal resistor (R ₁₄₎ of the tri-state buffer 12 It is configured by connecting to the DC level terminal of (3), and the operation and effect of the present invention thus constructed will be described in detail as follows.

As described in FIG. 1, the color difference signals BY and RY decoded by the decoding integrated device 2 are clamped by the clamp circuit unit 3, are selected by the multiplexer 4, and then the analog / digital converter 5 Is converted into a digital signal and then applied to the memory controller 6. At this time, when the digital signal data input to the memory controller 6 corresponds to the clamp center positive center value of the two color difference signals, a binary signal of 100000 is input to the data discrimination bit signal terminals B ₆ to B ₁ , and the digital signal is input. When the signal data becomes larger or smaller than the clamp level positive median of the two color difference signals, a binary signal larger or smaller than 100000 is input to the data discrimination bit signal terminals B ₆ to B _{1 in} proportion thereto.

Therefore, when the data signal corresponds to the positive center value of the clamp level and a signal of 100000 is input to the data discrimination bit signal terminals B ₆ to B ₁ , the low potential signal is output from the inverter I ₁ to generate the tri-state buffer 12. Is applied to one input terminal of NOR ₁ and the NOR gate NOR ₁ . Therefore, at this time, since the low potential signal is applied to all of the input terminals of the NOR gate NOR ₁ , a high potential signal is output to its output terminal and applied to the input terminal of the NOR gate NOR ₂ . As a result, a low potential signal is output to the output terminal of the NOR gate NOR ₂ and applied to the control terminal C of the tri state buffer 12 regardless of the signal applied to the other input terminal thereof. 12 is cut off to a high impedance state. At this time, the voltages of the analog / digital reference high and low voltage terminals (V _rh ) and (V _r1 ) are passed through the resistors R ₁₁ and R ₁₂ , and then the resistors R ₁₃ and the diode D ₁₂ are again turned on. The capacitor C ₁₁ is charged to maintain a predetermined level. In this way, the voltage charged in the capacitor C ₁₁ is applied to the DC level terminal of the clamp circuit portion 3 and applied as the clamp level voltage.

On the other hand, if the data signal corresponds to a value lower than the center value of the clamp level and a signal lower than 100000 is input to the data discrimination bit signal terminals B ₆ to B ₁ , for example, if the 11111 signal is input, the inverter I ₁ The high potential signal is output to the output terminal of and applied to the input terminal of the tri-state buffer 12 and the one input terminal of the NOA gate NOR ₁ . Therefore, at this time, the low potential signal is output to the output terminal of the NOR gate NOR ₁ and applied to one input terminal of the NOR gate NOR ₂ regardless of the signal applied to the other input terminal. Therefore, at this time, when the low potential signal is applied to the enable mode signal terminal S ₁ , the analog / digital clamp pulse signal terminal S ₂ , and the color signal selection mode signal terminal S ₃ , a high voltage is applied at the NOA gate NOR ₂ . The upper signal is outputted and applied to the control terminal C of the tri state buffer 12. As a result, the tri state buffer 12 is in a conductive state, and the high state signal applied to the input side thereof is applied to the tri state buffer 12. ) to be outputted through, thereby the high potential signal is applied to the capacitor (C ₁₁₎ through a resistor (R ₁₄₎ is the charging voltage level increases in the capacitor (C _11), raising the clamp level of the clamp circuit (3) do.

On the contrary, if the data signal corresponds to a value higher than the center value of the clamp level and a signal higher than 100000 is input to the data discrimination bit signal terminals B ₆ to B ₁ , for example, if a 100001 signal is input, Likewise, the low potential signal is output to the output terminal of the inverter I ₁ , and the low potential signal is output to the output terminal of the NOA gate NOR ₁ . Accordingly, when the low potential signal is applied to the enable mode signal terminal S ₁ , the analog / digital clamp pulse signal terminal S ₂ , and the color signal selection mode signal terminal S _{3 as} described above, the tri-state buffer 12 is applied. Is conducted and a low potential signal is output to the output side thereof, and thus the charging voltage of the capacitor C ₁₁ is discharged to the output side of the tri-state buffer 12 through the resistor R ₁₄ , and the level of the charging voltage is lowered. The clamp level of the clamp circuit portion 3 is lowered.

Also, the resistors R ₁₁ to R ₁₃ and the diodes D ₁₁ and D _{12 of the} limiter and the integrator 13 can stabilize the DC level at the initial power supply, and compensate for excessive level changes in the transient period. It becomes possible.

As described in detail above, the present invention compensates the clamp level of the clamp circuit by determining whether the data signal output from the analog / digital converter and applied to the memory controller corresponds to the appropriate level of the clamp. It is possible to compensate for the distortion, and it is possible to compensate even if the reference voltage of the analog / digital converter changes transiently or is unstable, and also it is possible to compensate for the defect of the clamp circuit part itself, so that the color is excellent. It is effective.

In addition, the integrator and the reducer circuit can stabilize the DC level at the beginning of power supply, and can compensate for excessive clamp level changes in the transient period.

Claims (2)

Low pass filter 1 for separating color subcarriers from video signal VS, and decoding integrated element 2 for separating color signals output from the low pass filter 1 into color difference signals BY and RY. And a clamp circuit section 3 for matching the color difference signals BY and RY output from the decoding integrated element 2 to the DC level by the clamp pulse signal CP of the memory controller 6, and the clamp circuit section. A multiplexer 4 which sequentially selects and outputs the color difference signal output from (3) by the selection control signal of the memory controller 6, and converts the signal selected and output from the multiplexer 4 into a digital signal, A circuit comprising an analog / digital converter 5 for outputting and a memory controller 6 for reducing and enlarging a video signal in response to an output signal of the analog / digital converter 5, in which the memory controller 6 is connected. Day of digital signal input A high impedance state or output a high potential or low potential signal according to the data level discrimination logic section 11 and the discrimination signal of the data level discrimination logic section 11, which determine whether the signal corresponds to an appropriate value of the clamp level. And a limiter and an integrator 13 for applying a DC voltage of a predetermined level to the clamp circuit unit 3 according to the tri state buffer 12 and the output signal state of the tri state buffer 12. Clamp correction circuit for color difference signals. The data level discrimination logic unit 11 is configured to pass the data discrimination bit signal terminal B ₆ to the one side input terminal of the NOR gate NOR ₁ and the tri state buffer 12 through the inverter I ₁ . a common junction box as well as access the data determination bit signal terminals (B ₅ ~ B ₁₎ to the other input terminal of the NOR gate (NOR ₁₎ on the input side, and connected to the other input terminal of the NOR gate (NOR _1), and Connect the output terminal of the noble gate (NOR ₁ ) and the enable mode signal terminal (S ₁ ), the analog / digital clamp pulse signal terminal (S ₂ ), and the color signal selection mode signal terminal (S ₃ ) to the noble gate (NOR ₂ ). And the control terminal (C) of the tri-state buffer (12) through the clamp correction circuit of the color difference signal.

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