JP2006005638A - Video signal input detection circuit, video signal switching apparatus, and video signal reproducing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a video signal input detection circuit for detecting a video signal by reducing the circuit scale without using a synchronizing chip clamping circuit . <P>SOLUTION: When a selection signal S1 is negated, a switch SW6 is turned off to turn off a pedestal clamp circuit, and a switch SW5 is turned on to connect a reference voltage VREF2 to a resistor R1 with a voltage follower 14 in the pedestal clamp circuit 11 as a buffer, thus composing an average value clamp circuit by a capacitor C1 having input coupling capacity and the resistor R1. A comparator 15 compares voltage with a threshold voltage VREF4 in the video signal, where an S video signal SIG1 is subjected to average value clamped by the reference voltage VREF2, and detects whether the S video signal SIG1 is inputted. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a video signal input detection circuit for detecting whether or not a video signal is input.

  In a television receiver, a video tape recorder, and the like, a video signal source selected by a viewer is selected and reproduced using a remote controller or the like. The video signal source includes a composite video signal and an S video signal (Separate video signal). The composite video signal is a signal in which the luminance signal and the color signal are mixed, whereas the S video signal is separated from the luminance signal and the color signal. Less likely to cause color problems. Therefore, in a television receiver, a video tape recorder, etc., even when the S video signal is not selected (when the composite video signal is selected), the presence or absence of the S video signal is detected, and the S video signal is detected. In many cases, a function of automatically switching to the S video signal is provided.

  As a conventional technique for detecting an S video signal, there is, for example, Patent Document 1. Patent Document 1 discloses a description of a video signal identification circuit that detects an S video signal of S2 standard by EIAJ (Electronic Industries Association of Japan). Specifically, only the component is removed from the superimposed video signal in which the identification signal having three voltage ranges of 0 V, 1.4 to 2.4 V, and 3.5 to 5 V is superimposed on the S2 standard chroma signal. An identification signal is extracted. The extracted identification signal is compared with two preset reference voltages, the image form is identified based on the comparison results, and whether the reference terminal of the S video terminal is connected to the installation line or not is determined. The determination is made to detect whether or not an S video signal has been input.

JP-A-10-136387

  However, the prior art described in Patent Document 1 detects the connection state of the S video terminal and identifies the three standards of the S video signal. In order to detect the composite video signal, the composite video signal A dedicated circuit must be provided separately.

  A conventional video signal input detection circuit that detects a composite video signal and an S video signal with a circuit having the same configuration is a pedestal clamp circuit that clamps the video signal at the time of selection (when the video signal is played back), and is not selected A sync chip clamp circuit that clamps a video signal at the time (when no video signal is input or when playback is not performed even when a video signal is input), and a comparator that detects the presence or absence of the video signal .

  When inputting a video signal, a clamp circuit for holding the black level at a constant DC voltage is necessary. Even when the presence or absence of the video signal is detected, the voltage of the clamped video signal with a small DC voltage fluctuation is predetermined. The threshold voltage is compared with a comparator.

  Since the pedestal clamp circuit is controlled by a synchronization signal (clamp pulse) of the video signal, the video signal cannot be clamped when the clamp pulse is asynchronous. For this reason, the video signal is clamped by operating the pedestal clamp circuit when selected, and the video signal is detected by clamping the video signal by operating the sync tip clamp circuit when not selected.

  Thus, a conventional video signal input detection circuit that detects a composite video signal and an S video signal with a circuit having the same configuration needs to include a pedestal clamp circuit that operates when selected and a sync chip clamp circuit that operates when not selected. There is a problem that the circuit scale becomes large.

  The present invention has been made in view of the above, and an object thereof is to obtain a video signal input detection circuit for detecting a video signal by reducing the circuit scale without using a sync chip clamp circuit.

  In order to solve the above-described problems and achieve the object, a video signal input detection circuit according to the present invention is a video signal input detection circuit that detects the presence or absence of a video signal. And a pedestal clamp circuit that clamps the black level of the video signal to a constant voltage when the clamp pulse generated using the synchronization signal of the video signal input from the outside is asserted, and the selection signal is negated In this case, an average value clamp circuit that clamps the average value of the video signal to a constant voltage, and whether or not the video signal is input using the video signal clamped by the pedestal clamp circuit or the average value clamp circuit. And a comparator that outputs a detection signal when a video signal is input. .

  According to the video signal input detection circuit of the present invention, when the selection signal input from the outside is asserted, the video signal is detected using the video signal obtained by clamping the black level of the video signal to a constant voltage by the pedestal clamp circuit. The presence / absence of the video signal is detected by using the video signal obtained by clamping the average value of the video signal to a constant voltage by the average value clamp circuit when the selection signal is negated. Compared with the case where a clamp circuit is used, the circuit scale can be reduced.

  Embodiments of a video signal input detection circuit and a video signal switching device according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

  An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing an example of a video signal switching device to which a video signal input detection circuit according to an embodiment of the present invention is applied. The video signal input detection circuit and the video signal switching device according to the present invention are used in a video signal reproducing device for reproducing a video signal such as a television receiver or a video tape recorder. The video signal switching device shown in FIG. 1 includes a plurality (three in this case) of video signal input detection circuits 10a to 10c, a control circuit 30, and a selector 50.

  The video signal input detection circuits 10a to 10c operate as pedestal clamp circuits or average value clamp circuits based on the selection signals S1 to S3 and the clamp pulses SYNC11 to SYNC13 input from the control circuit 30, and the video signals SIG1 to SIG3 are generated. It has a function to detect whether it is input.

  The video signal input detection circuit 10a detects whether or not the S video signal SIGN1 is input based on the selection signal S1 and the clamp pulse SYNC11 input from the control circuit 30, and outputs the detection signal SYNC1 to the control circuit 30. The video signal SIG11 obtained by clamping the S video signal SIG1 is output to the selector 50. Here, the S video signal SIG1 is a luminance signal of the S video signal.

  The video signal input detection circuit 10b detects whether or not the composite video signal SIGN2 is input based on the selection signal S2 and the clamp pulse SYNC12 input from the control circuit 30, and outputs the detection signal SYNC2 to the control circuit 30. The video signal SIG12 obtained by clamping the composite video signal SIG2 is output to the selector 50.

  The video signal input detection circuit 10c detects whether or not the composite video signal SIGN3 is input based on the selection signal S3 and the clamp pulse SYNC13 input from the control circuit 30, and outputs the detection signal SYNC3 to the control circuit 30. The video signal SIG13 obtained by clamping the composite video signal SIG3 is output to the selector 50.

  The video signal input detection circuits 10a to 10c are composed of the same circuit. The circuit configuration of the video signal input detection circuit will be described in detail with reference to the circuit diagram showing the configuration of the video signal input detection circuit 10a shown in FIG.

  The video signal input detection circuit 10a includes a capacitor C1 having an input coupling capacitance, a resistor R1, five switches SW1 to SW5, an inverter 12, an AND gate 13, a switch SW6, and a voltage follower 14, and a comparator. 15 is provided.

  The switches SW1 and SW2 are controlled by the selection signal S1, and the reference voltage VREF1 (first reference voltage in the claims) or the reference voltage VREF2 (in the claims) is applied to the voltage follower 14 in the pedestal clamp circuit 11. The second reference voltage) is output. Specifically, the switch SW1 is turned on when the selection signal S1 is asserted (in this case, “H”), and turned off when the selection signal S1 is negated (in this case, “L”). The switch SW2 is controlled by the selection signal S1 via the inverter 12, and is turned off when the selection signal S1 is “H” and turned on when the selection signal S1 is “L”. Therefore, the voltage follower 14 is supplied with the reference voltage VREF1 when the selection signal S1 is “H”, and the reference voltage VREF2 when the selection signal S1 is “L”.

  The switches SW3 and SW4 are controlled by the selection signal S1, and the comparator 15 that detects the synchronization of the clamped video signal SIG11 has a threshold voltage VREF3 (first threshold voltage in the claims) that serves as a threshold for synchronization detection. ) Or a threshold voltage VREF4 (second threshold voltage in the claims). Specifically, the switch SW3 is turned on when the selection signal S1 is “H”, and turned off when the selection signal S1 is “L”. The switch SW4 is controlled by the selection signal S1 via the inverter 12, and is turned off when the selection signal S1 is “H”, and turned on when the selection signal S1 is “L”. Therefore, the threshold voltage VREF3 is input to the comparator 15 when the selection signal S1 is “H”, and the threshold voltage VREF4 is input when the selection signal S1 is “L”.

  The pedestal clamp circuit 11 is controlled by the selection signal S1 and the clamp pulse SYNC11, and when the S video signal SIG1 is selected by the control circuit 30, the S video signal SIG1 is clamped (pedestal clamp) by the reference voltage VREF1. Specifically, when the selection signal S1 is “H” by the AND gate 13 and the clamp pulse SYNC11 is asserted (in this case “H”), the switch SW6 is turned ON, and the S video is generated by the reference voltage VREF1. The signal SIG1 is clamped. When the selection signal S1 or the clamp pulse SYNC11 is negated (in this case, “L”), the switch SW6 is turned OFF, and the pedestal clamp of the S video signal SIG1 is not performed. As will be described later, the clamp pulse SYNC11 is a signal generated by the horizontal synchronization signal of the S video signal SIG1, and the pedestal clamp circuit 11 clamps the black level by the reference voltage VREF1 when the S video signal SIG1 is selected. is doing.

  The switch SW5 is controlled by the selection signal S1 through the inverter 12, and is turned off when the selection signal S1 is “H”, and is turned on when the selection signal S1 is “L” to output the voltage follower 14. Connect to resistor R1. That is, the switch SW5 clamps (average value clamp) the S video signal SIG1 with the reference voltage VREF2 output from the voltage follower 14 when the selection signal S1 is “L”. That is, when the switch SW5 is turned on, the capacitor C1 and the resistor R1 form an average value clamp circuit by the reference voltage VREF2 buffered by the voltage follower 14.

  The comparator 15 compares the clamped video signal SIG11 with the threshold voltage VREF3 or the threshold voltage VREF4 to detect the S video signal.

  Returning to FIG. 1, the control circuit 30 is composed of, for example, a logic and a microprocessor, and the S video based on the detection signals SYNC1 to SYNC3 input from the video signal input detection circuits 10a to 10c and a predetermined priority order. One of the signal SIG1 and the composite signals SIG1 and SIG2 is selected, and the selection signals S1 to S3 are output to the video signal input detection circuits 10a to 10c and the selector 50.

  Further, the control circuit 30 clamps each horizontal synchronization signal inverted based on a horizontal synchronization signal input from a synchronization detection circuit that detects horizontal synchronization signals of the S video signal SIG1 and the composite video signals SIG2 and SIG3 (not shown). Pulses SYNC11 to SYNC13 are generated. The control circuit 30 outputs the generated clamp pulses SYNC11 to SYNC13 to the video signal input detection circuits 10a to 10c.

  The selector 50 selects any one of the video signals SIG11 to SIG13 input from the video signal input detection circuits 10a to 10c based on the selection signals S1 to S3 input from the control circuit 30, and selects the selected video signal. SIG11 to SIG13 are output as video signals to be reproduced.

  Next, referring to FIG. 3 to FIG. 5, the operation of the video signal input detection circuit according to the present embodiment of the present invention is exemplified by the video signal input detection circuit 10a corresponding to the S video signal SIG1 shown in FIG. Will be described.

  Assume that the viewer selects the composite video signal SIG3 with the remote controller. The control circuit 30 selects the video signal input detection circuit 10c corresponding to the composite video signal SIG3, and sets the selection signals S1 and S2 to “L” and the selection signal S3 to “H”. Thus, the selector 50 selects the video signal SIG13 input from the video signal input detection circuit 10c and outputs the video signal SIG13 as a video signal to be reproduced.

  Since the selection signal S1 of the switches SW1 to SW6 of the video signal input detection circuit 10a is “L”, the switches SW1, SW3, SW6 are turned off and the switches SW2, SW4, SW5 are turned on. Since the switch SW1 is OFF and the switch SW2 is ON, the reference voltage VREF2 is input to the voltage follower 14. In addition, since the switch SW5 is ON and the switch SW6 is OFF, the video signal input detection circuit 10a has the reference that the voltage follower 14 in the pedestal clamp circuit 11 is buffered by the pedestal clamp circuit 11 being OFF. The voltage VREF2 operates as an average value clamp circuit that clamps the S video signal SIG1 to an average voltage by the resistor R1 and the capacitor C1.

  On the other hand, since the switch SW3 is OFF and the switch SW4 is ON, the threshold voltage VREF4 is input to the comparator 15. The comparator 15 compares the threshold voltage VREF4 with the voltage of the average-clamped video signal SIG11 and detects the S video signal.

  FIG. 3 shows waveforms of the clamped video signal SIG11 and the detection signal SYNC1 when the S video signal SIG1 is not input (no signal). As shown in FIG. 3, the DC voltage indicating no signal is clamped by the average value by the reference voltage VREF2, and becomes the video signal SIG11 of the reference voltage VREF2. The reference voltage VREF2 is set in advance so that the reference voltage VREF2> the threshold voltage VREF4 is satisfied. Therefore, when the S video signal SIG1 is not input (when there is no signal), the voltage of the clamped video signal SIG11 is higher than the threshold voltage VREF4. The comparator 15 negates the detection signal SYNC1 (in this case, “H”).

  FIG. 4 shows waveforms of the clamped video signal SIG11 and the detection signal SYNC1 when an all white signal is input to the S video signal SIG1. As shown in FIG. 4, the S video signal SIG1 indicating the all white signal is clamped by the reference voltage VREF2 by the average value clamp circuit. The comparator 15 compares the threshold voltage VREF4 with the voltage of the clamped video signal SIG11, and asserts the detection signal in the period 71 when the voltage of the clamped video signal SIG11 is lower than the threshold voltage VREF4 (in this case, “L ") In the period 72 in which the voltage of the clamped video signal SIG11 is equal to or higher than the threshold voltage VREF4, the detection signal is set to" H ".

  FIG. 5 shows waveforms of the clamped video signal SIG11 and the detection signal SYNC1 when an all black signal is input to the S video signal SIG1. As shown in FIG. 5, the S video signal SIG1 indicating the all black signal is clamped by the reference voltage VREF2 by the average value clamp circuit. The comparator 15 compares the threshold voltage VREF4 with the voltage of the clamped video signal SIG11, and the detection signal is clamped to “L” in the period 71 in which the voltage of the clamped video signal SIG11 is lower than the threshold voltage VREF4. In the period 72 in which the voltage of the video signal SIG11 is equal to or higher than the threshold voltage VREF4, the detection signal is set to “H”.

  Here, it is assumed that a signal is input to the S video signal SIG1 that is no signal. The comparator 15 compares the clamped video signal SIG11 and the threshold voltage VREF4, and during the period when the voltage of the clamped video signal SIG11 is lower than the threshold voltage VREF4, the comparator 15 is clamped by setting the detection signal SYNC1 to “L”. The detection signal SYNC1 is set to “H” during the period when the voltage of the video signal SIG11 is equal to or higher than the threshold voltage VREF4.

  Even when the detection signal SYNC3 is input from the currently selected video signal input detection circuit 10c, the control circuit 30 receives the detection signal SYNC1 input from the video signal input detection circuit 10a corresponding to the S video signal SIGN1. When it is indicated that the S video signal is input, that is, when it is detected that the detection signal SYNC1 becomes “L”, it is determined to select the video signal input detection circuit 10a. The control circuit 30 changes the selection signal S1 from “L” to “H” and changes the selection signal S3 from “H” to “L”. That is, the video signal input detection circuit 10c corresponding to the composite video signal SIG3 is switched to the video signal input detection circuit 10c corresponding to the S video signal SIG1.

  When the selection signal S1 becomes “H” and the selection signal S3 becomes “L”, the selector 50 outputs the video signal SIG11 input from the video signal input detection circuit 10a as a video signal to be reproduced.

  When the selection signal S1 changes from “L” to “H”, the switches SW1 and SW3 of the video signal input detection circuit 10a are turned on, and the switches SW2, SW4 and SW5 are turned off. Since the switch SW1 is ON and the switch SW2 is OFF, the reference voltage VREF1 is input to the voltage follower 14. The switch SW6 is ON only when the clamp pulse SYNC11 is “H”, and is OFF when the clamp pulse SYNC11 is “L”. Since the switch SW5 is turned off, the video signal input detection circuit 10a is controlled by the clamp pulse SYNC11 and operates as a pedestal clamp circuit that pedestal clamps the black level of the S video signal SIG1 by the reference voltage VREF1.

  On the other hand, since the switch SW3 is ON and the switch SW4 is OFF, the comparator 15 detects the S video signal by comparing the threshold voltage VREF3 with the voltage of the pedestal clamped video signal SIG11.

  Thus, in this embodiment, when not selected, the voltage follower 14 in the pedestal clamp circuit 11 is used as a buffer to connect the reference voltage VREF2 to the resistor R1, so that the capacitor C1 having the input coupling capacitance and the resistor R1 are connected. Since the video signal obtained by clamping the average value of the video signal input by the reference voltage VREF2 is generated, the video signal can be average clamped without using the sync chip clamp circuit, and the video signal input detection circuit The circuit scale can be reduced.

  In this embodiment, since the reference voltage for clamping the video signal and the threshold voltage for detecting the presence / absence of the video signal are switched between selection and non-selection, the presence / absence of the video signal is accurately determined. Can be detected.

  In this embodiment, when the S video signal is input, the control circuit 30 switches from the currently selected composite video signal to the S video signal. can do.

  In this embodiment, the case where priority is given to the S video signal when the composite video signal and the S video signal are detected has been described as an example. However, the control circuit 30 detects a plurality of composite video signals. In this case, the video signal can be automatically switched even when there are a plurality of composite video signal input terminals.

  As described above, the video signal input detection circuit according to the present invention is useful for a video playback device to which a plurality of video signal sources are input, and in particular, a video playback device to which an S video signal and a composite video signal are input. Suitable for

It is a block diagram which shows an example of the video signal switching apparatus with which the video signal input detection circuit of embodiment concerning this invention is applied. FIG. 2 is a circuit diagram showing a configuration of a video signal input detection circuit shown in FIG. 1. It is a figure which shows the waveform of the clamped video signal and detection signal in case the S video signal is not input. It is a figure which shows the waveform of the clamped video signal and detection signal when an all-white signal is input to the S video signal. It is a figure which shows the waveform of the clamped video signal and detection signal when an all black signal is input into S video signal.

Explanation of symbols

10a, 10b, 10c Video signal input detection circuit 11 Pedestal clamp circuit 12 Inverter 13 AND gate 14 Voltage follower 15 Comparator 30 Control circuit 50 Selector SW1, SW2, SW3, SW4, SW5, SW6 Switch C1 Capacitor R1 Resistance

Claims (6)

In the video signal input detection circuit that detects the presence or absence of a video signal,
When the selection signal input from the outside is asserted and the clamp pulse generated using the synchronization signal of the video signal input from the outside is asserted, the black level of the video signal is clamped to a constant voltage. A pedestal clamp circuit to
When the selection signal is negated, an average value clamp circuit that clamps the average value of the video signal to a constant voltage;
A comparator that outputs a detection signal when a video signal is input by determining whether the video signal is input using the video signal clamped by the pedestal clamp circuit or the average value clamp circuit;
A video signal input detection circuit comprising: The pedestal clamp circuit is:
A voltage follower that outputs a first reference voltage when the selection signal is asserted, and outputs a second reference voltage when the selection signal is negated;
A switch that clamps the video signal with a first reference voltage output by the voltage follower when the selection signal is asserted and the clamp pulse is asserted;
With
The average value clamp circuit is:
When the selection signal is negated, the video signal is clamped by the second reference voltage output by the voltage follower;
The video signal input detection circuit according to claim 1. The comparator is
When the selection signal is asserted, the first threshold voltage is compared with the voltage of the video signal clamped by the pedestal clamp circuit. When the selection signal is negated, the second threshold voltage and the average value clamp circuit are compared. Comparing the voltage of the video signal clamped by the detection of the presence or absence of the video signal;
The video signal input detection circuit according to claim 1, wherein: A video signal switching device for switching a plurality of video signals,
The video signal input detection circuit according to any one of claims 1 to 3, corresponding to the plurality of video signals;
A control circuit for selecting a video signal to be reproduced from the plurality of video signals and outputting a selection signal based on the detection signals input from these video signal input detection circuits;
A selector that outputs a video signal clamped by a video signal input detection circuit corresponding to the video signal indicated by the selection signal;
A video signal switching device comprising: The control circuit includes:
When detection signals are input from a plurality of video signal input detection circuits, selecting a video signal based on a predetermined priority order;
A video signal switching device. 6. A video signal reproducing device comprising the video signal switching device according to claim 4.

Images