KR960011814B1 - Method for manufacturing a semiconductor memory cell - Google Patents
Method for manufacturing a semiconductor memory cell Download PDFInfo
- Publication number
- KR960011814B1 KR960011814B1 KR92021658A KR920021658A KR960011814B1 KR 960011814 B1 KR960011814 B1 KR 960011814B1 KR 92021658 A KR92021658 A KR 92021658A KR 920021658 A KR920021658 A KR 920021658A KR 960011814 B1 KR960011814 B1 KR 960011814B1
- Authority
- KR
- South Korea
- Prior art keywords
- polysilicon
- depositing
- gate
- forming
- bpsg
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 7
- 229920005591 polysilicon Polymers 0.000 abstract 7
- 238000000151 deposition Methods 0.000 abstract 5
- 239000005380 borophosphosilicate glass Substances 0.000 abstract 3
- 238000005530 etching Methods 0.000 abstract 2
- 239000002184 metal Substances 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
forming a gate by a gate polysilicon after depositing a gate oxide and the gate polysilicon on a semiconductor substrate; forming a lightly-doped source/drain region and forming a side wall on the side of the gate by etchback of an oxide; forming a highly-doped source/drain and depositing a first polysilicon and etching the first polysilicon to reveal the drain region; defining a bit line contact hole by depositing a photoresist after depositing a dielectric, a second polysilicon and a BPSG; etching the BPSG, the second polysilicon and the dielectric to reveal the drain region; reflowing to oxidize the revealed side of the second polysilicon; and depositing a metal on top of the BPSG.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR92021658A KR960011814B1 (en) | 1992-11-18 | 1992-11-18 | Method for manufacturing a semiconductor memory cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR92021658A KR960011814B1 (en) | 1992-11-18 | 1992-11-18 | Method for manufacturing a semiconductor memory cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940012612A KR940012612A (en) | 1994-06-24 |
| KR960011814B1 true KR960011814B1 (en) | 1996-08-30 |
Family
ID=19343344
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR92021658A KR960011814B1 (en) | 1992-11-18 | 1992-11-18 | Method for manufacturing a semiconductor memory cell |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR960011814B1 (en) |
-
1992
- 1992-11-18 KR KR92021658A patent/KR960011814B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR940012612A (en) | 1994-06-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| G160 | Decision to publish patent application | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20050721 Year of fee payment: 10 |
|
| LAPS | Lapse due to unpaid annual fee |