KR960011720A - Parallel Processing Method in One-to-Many Master-Slave Computing Units - Google Patents

Parallel Processing Method in One-to-Many Master-Slave Computing Units Download PDF

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Publication number
KR960011720A
KR960011720A KR1019940023457A KR19940023457A KR960011720A KR 960011720 A KR960011720 A KR 960011720A KR 1019940023457 A KR1019940023457 A KR 1019940023457A KR 19940023457 A KR19940023457 A KR 19940023457A KR 960011720 A KR960011720 A KR 960011720A
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South Korea
Prior art keywords
cpu
master
slave
parallel processing
processing method
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KR1019940023457A
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Korean (ko)
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KR0123855B1 (en
Inventor
김준우
오학서
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김광호
삼성전자 주식회사
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Priority to KR1019940023457A priority Critical patent/KR0123855B1/en
Publication of KR960011720A publication Critical patent/KR960011720A/en
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Publication of KR0123855B1 publication Critical patent/KR0123855B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

본 발명은 일대다 마스터-슬레이브 방식 연산장치에서의 병렬처리 방법에 관한 것이다.The present invention relates to a parallel processing method in a one-to-many master-slave operation unit.

본 발명은 대상 시스템에 관련되는 변수들에 초기값을 설정하는 단계, 마스터 CPU로부터 특정 슬레이브 CPU에 소정의 작업을 지시하는 단계, 지시받은 작업을 수행하고 결과를 DPRAM에 기록한 후, 마스터 CPU로 인터럽트를 걸어주는 단계, 및 상기 슬레이브 CPU에 지시한 작업이 완료되면 작업지시 구조체에 대한 포인터 변수를 0(zero)화 하는 단계를 포함하여 된 점에 특징이 있다. 따라서, 특정 슬레이브 CPU의 번호를 기억할 필요가 없고, 객체 지향적인 프로그래밍을 할 수 있으며, 리턴 인자를 불러오기 위해 일일이 프로그래밍해야 하는 번거로움이 없을 뿐만 아니라, 응용프로그래밍의 소스 코드의 길이를 줄여 프로그램을 한층 단순화시킬 수 있다.The present invention sets an initial value to variables related to a target system, instructs a predetermined task from a master CPU to a specific slave CPU, performs an instruction and writes a result to a DPRAM, and then interrupts the master CPU. And a zeroing of the pointer variable for the work instruction structure when the operation instructed to the slave CPU is completed. Thus, there is no need to remember the number of a specific slave CPU, object-oriented programming, no hassles to program manually to retrieve the return arguments, and shorten the length of the source code of the application programming. It can be further simplified.

Description

일대다 마스터-슬레이브 방식 연산장치에서의 병렬처리 방법Parallel Processing Method in One-to-Many Master-Slave Computing Units

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 종래 일대다 마스터-슬레이브 방식 컴퓨터 시스템의 개략적인 장치 구성도.1 is a schematic device diagram of a conventional one-to-many master-slave computer system.

*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 마스터 CPU11: master CPU

12a, 12b, 12r, 12s : 슬레이브 CPU12a, 12b, 12r, 12s: slave CPU

13a, 13b, 13r, 13s : DPRAM13a, 13b, 13r, 13s: DPRAM

Claims (2)

대상 시스템에 관련되는 변수들에 초기값을 설정하는 단계, 마스터 CPU로부터 특정 슬레이브 CPU에 소정의 작업을 지시하는 단계, 지시받은 작업을 수행하고 결과를 DPRAM에 기록한 후, 마스터 CPU로 인터럽트를 걸어주는 단계, 및 상기 슬레이브 CPU에 지시한 작업이 완료되면 작업지시 구조체에 대한 포인터 변수(job pointer)를 0(zero)화 하는 단계를 포함하여 된 것을 특징으로 하는 일대다 마스터-슬레이브 방식 연산장치에서의 병렬처리 방법.Setting an initial value to variables related to the target system, instructing a specific slave CPU from a predetermined task, performing a designated task, writing a result to DPRAM, and interrupting the master CPU. In the one-to-many master-slave operation unit, characterized in that it comprises the step of zeroing a pointer variable (job pointer) for the work instruction structure when the job instructed to the slave CPU is completed. Parallel processing method. 제 1항에 있어서, 상기 마스터 CPU가 슬레이브 CPU에게 지시할 작업의 내용과 리턴되는 결과 및 작업의 완료여부를 하나의 구조체 및 그를 가리키는 변수데이타로 저장하여 그 작업의 지시를 위한 함수에 인자로서 포함시켜 호출하는 방식을 지닌 모듈의 구동프로그램의 일부로 포함하는 방식으로 된 것을 특징으로 하는 일대다 마스터-슬레이브 방식 연산장치에서의 병렬처리 방법.The method of claim 1, wherein the master CPU stores the contents of the task to be instructed to the slave CPU, the result to be returned, and whether the task is completed as a structure and variable data indicating the same and included in the function for the instruction of the task. A parallel processing method in a one-to-many master-slave type computing device, characterized in that it is included as part of a drive program of a module having a method of calling. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940023457A 1994-09-15 1994-09-15 The method of parallel processing for one to master slave KR0123855B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940023457A KR0123855B1 (en) 1994-09-15 1994-09-15 The method of parallel processing for one to master slave

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940023457A KR0123855B1 (en) 1994-09-15 1994-09-15 The method of parallel processing for one to master slave

Publications (2)

Publication Number Publication Date
KR960011720A true KR960011720A (en) 1996-04-20
KR0123855B1 KR0123855B1 (en) 1997-12-09

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KR1019940023457A KR0123855B1 (en) 1994-09-15 1994-09-15 The method of parallel processing for one to master slave

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100619303B1 (en) * 1997-07-25 2006-09-05 피지컬 옵틱스 코포레이션 Method of rapid prototyping for multifaceted and/or folded path lighting systems

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100619303B1 (en) * 1997-07-25 2006-09-05 피지컬 옵틱스 코포레이션 Method of rapid prototyping for multifaceted and/or folded path lighting systems

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KR0123855B1 (en) 1997-12-09

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