KR960011686A - Data processor with data bus and instruction fetch bus provided separately from each other - Google Patents

Data processor with data bus and instruction fetch bus provided separately from each other Download PDF

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Publication number
KR960011686A
KR960011686A KR1019950030242A KR19950030242A KR960011686A KR 960011686 A KR960011686 A KR 960011686A KR 1019950030242 A KR1019950030242 A KR 1019950030242A KR 19950030242 A KR19950030242 A KR 19950030242A KR 960011686 A KR960011686 A KR 960011686A
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KR
South Korea
Prior art keywords
data
bus
provided separately
buses
data processor
Prior art date
Application number
KR1019950030242A
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Korean (ko)
Other versions
KR100186847B1 (en
Inventor
히데키 스기모토
Original Assignee
가네꼬 히사시
닛폰 덴키 가부시끼가이샤
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Publication of KR960011686A publication Critical patent/KR960011686A/en
Application granted granted Critical
Publication of KR100186847B1 publication Critical patent/KR100186847B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/27—Built-in tests
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Microcomputers (AREA)
  • Debugging And Monitoring (AREA)
  • Information Transfer Systems (AREA)
  • Hardware Redundancy (AREA)

Abstract

데이타 처리기는 서로가 분리되어 제공된 내부 데이타 버스와 명령어 패치 버스를 가진다. 데이타 판독 작동 모드가 지정될 때 내부 판독 전용 메모리에 저장된 데이타는 내부 데이타 버스와 명령어 페치 버스로 판독되고 이러한 버스의 데이타는 그들 사이의 일치와 외부로 전송된 비교 결과 신호를 체크하는 실행 장치에 의한 작용에 영향을 받는다.The data processors have internal data buses and instruction patch buses provided separately from each other. When the data read operation mode is specified, the data stored in the internal read-only memory is read into the internal data bus and the command fetch bus, and the data on these buses are executed by the execution device which checks the match between them and the comparison result signal sent outward. Affected by action.

Description

서로 분리되어 제공되는 데이타 버스와 명령어 페치 버스를 가지는 데이타 처리기.Data processor with data bus and instruction fetch bus provided separately from each other.

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 1 도는 본 발명의 제 1 실시예에 따른 데이타 처리기를 도시하는 블록도.1 is a block diagram showing a data processor according to a first embodiment of the present invention.

제 2 도는 제 1 도에 도시된 바와 같은 데이타 처리기의 동작을 도시하는 타이밍도.FIG. 2 is a timing diagram illustrating the operation of a data processor as shown in FIG.

Claims (3)

데이타 처리기에 있어서, 데이타 저장 수단과, 데이타 버스와, 상기 내부 버스로 부터 분리되어 제공되는 명령어 버스와, 상기 저장 수단으로부터 판독된 데이타를 상기 데이타 버스와 상기 명령어 버스에 전송하는 전송 수단과, 상기 명령어 버스와 상기 데이타 버스에 연결되어 데이타에 관한 동작을 실행하고 동작 결과 신호를 발생하는 실행 수단을 구비하는 것을 특징으로 하는 데이타 처리기.A data processor comprising: a data storage means, a data bus, a command bus provided separately from the internal bus, transfer means for transferring data read from the storage means to the data bus and the command bus, And execution means connected to the command bus and the data bus to execute an operation on data and to generate an operation result signal. 데이타 처리기에 있어서, 데이타 저장 수단과, 서로 분리되어 제공되는 제 1 및 제 2 버스와, 상기 저장 수단으로 부터 판독된 데이타를 상기 제 1 버스에 전송하는 전송 수단과, 외부로부터의 데이타를 상기 제 2 버스에 전송하는 수단과, 상기 제 1 버스 및 제 2 버스의 데이타에 대한 동작을 실행하고 동작 결과 신호를 외부에 발생하는 실행 수단을 구비하는 것을 특징으로 하는 데이타 처리기.A data processor comprising: data storage means, first and second buses provided separately from each other, transfer means for transferring data read from the storage means to the first bus, and data from outside Means for transmitting to two buses, and executing means for executing an operation on data of the first bus and the second bus and generating an operation result signal to the outside. 제 2 항에 있어서, 상기 저장 수단으로부터의 데이타를 상기 제 2 버스에 전송하는 수단을 더 구비하는 것을 특징으로 하는 데이타 처리기.3. The data processor of claim 2, further comprising means for transferring data from said storage means to said second bus. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950030242A 1994-09-12 1995-09-12 Data processor having data bus and instruction fetch bus provided separately from each other KR100186847B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP94-243295 1994-09-12
JP6243295A JP2581018B2 (en) 1994-09-12 1994-09-12 Data processing device

Publications (2)

Publication Number Publication Date
KR960011686A true KR960011686A (en) 1996-04-20
KR100186847B1 KR100186847B1 (en) 1999-05-15

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US (2) US5706423A (en)
EP (1) EP0701210B1 (en)
JP (1) JP2581018B2 (en)
KR (1) KR100186847B1 (en)
DE (1) DE69511019T2 (en)

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JP2581018B2 (en) * 1994-09-12 1997-02-12 日本電気株式会社 Data processing device
FR2825490A1 (en) * 2001-05-29 2002-12-06 Koninkl Philips Electronics Nv VALIDATION DEVICE FOR AN INTEGRATED CIRCUIT
US7318169B2 (en) * 2002-05-15 2008-01-08 David Czajkowski Fault tolerant computer
US7237148B2 (en) * 2002-09-05 2007-06-26 David Czajkowski Functional interrupt mitigation for fault tolerant computer
JP2004185060A (en) * 2002-11-29 2004-07-02 Renesas Technology Corp Microcomputer
DE10302287A1 (en) * 2003-01-22 2004-08-12 Micronas Gmbh Storage device for a multibus architecture
US7260742B2 (en) * 2003-01-28 2007-08-21 Czajkowski David R SEU and SEFI fault tolerant computer
CN100545804C (en) * 2003-08-18 2009-09-30 上海海尔集成电路有限公司 A kind of based on the microcontroller of CISC structure and the implementation method of instruction set thereof
US7930683B2 (en) 2006-03-31 2011-04-19 Sap Ag Test automation method for software programs
KR100803690B1 (en) * 2006-08-10 2008-02-20 삼성전자주식회사 Electro-mechanical non-volatile memory device and method for manufacturing the same
CN101178644B (en) * 2006-11-10 2012-01-25 上海海尔集成电路有限公司 Microprocessor structure based on sophisticated instruction set computer architecture
US8381071B1 (en) * 2010-05-21 2013-02-19 Lsi Corporation Systems and methods for decoder sharing between data sets

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JPS5730016A (en) * 1980-07-31 1982-02-18 Hitachi Ltd Interface controlling system
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JP2581018B2 (en) * 1994-09-12 1997-02-12 日本電気株式会社 Data processing device

Also Published As

Publication number Publication date
JP2581018B2 (en) 1997-02-12
EP0701210B1 (en) 1999-07-28
US5706423A (en) 1998-01-06
DE69511019D1 (en) 1999-09-02
US5958074A (en) 1999-09-28
KR100186847B1 (en) 1999-05-15
DE69511019T2 (en) 2000-02-24
EP0701210A2 (en) 1996-03-13
JPH0883220A (en) 1996-03-26
EP0701210A3 (en) 1996-09-04

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