KR960010074B1 - Method of manufacturing a read only memory device - Google Patents

Abstract

The method is provided to recover defective cell without increasing the chip area, and comprises the steps of: detecting the location of a defective memory cell transistor during data recording; forming an opening for ion injection by etching the top of a protecting layer (211) of the defective memory cell transistor; forming a protecting layer (502) after recording data in the channel region by injecting ion through the opening.

Description

How to Resolve Defects in Read-Only Memory Devices

1 is a layout diagram and an equivalent circuit diagram of a general mask ROM.

2 is a manufacturing process diagram of FIG.

3 is a layout diagram of a mask ROM having a redundant cell array according to the prior art.

FIG. 4 is a partial circuit diagram of the FIG. 3 redundancy cell array.

5 is a first embodiment of a defect repair method according to the present invention.

6 is another embodiment according to the first embodiment.

7 is a second embodiment of a defect repair method according to the present invention.

8 is another embodiment according to the second embodiment.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a read-only memory device, and more particularly, to a method for repairing defects generated during a manufacturing process.

A read-only memory device is a memory device having a function of reading recorded data. In such a memory device, data is written during a manufacturing process. An example of such a read only memory device may be a mask read only memory. In the mask ROM, data designated by the user is recorded during the manufacturing process.

1 is a layout diagram and an equivalent circuit diagram showing a part of a cell array of a general mask ROM. (A) of FIG. 1 is a layout diagram of a part of a cell array, and (b) is an equivalent circuit diagram of (a). Referring to the configuration of FIG. 1, two column strings are connected to one bit line. Each cell string consists of n memory cell transistors and two string selectors. The mask ROM shown in FIG. 3 has n word lines 12 extending longitudinally over n ⁺ active region 11 formed on a substrate, and bit lines 13 extending laterally perpendicular to the word lines. And the contact area 14 which connects the bit line 13 and the lower n ⁺ active area 11 to each other at a predetermined position. In this case, the word line passing through the active region acts as an enhancement memory cell transistor via a gate oxide layer between the active region. The data write operation in the mask ROM is achieved by converting an incremental transistor into a depletion transistor by implanting ions into a channel region (a substrate region under the gate oxide film) of a memory cell. The ion implantation region 15 shown by a dotted line in FIG. 1 (a) is a region implanted with ions for conversion into a depletion transistor.

FIG. 2 is an example of a manufacturing process diagram of the cell array of FIG. 1, and (a) to (d) of FIG. 2 are cross-sectional views taken along the line AA 'of FIG. 1, and (a') to (d '). ) Is a cross-sectional view taken along the line B-B 'perpendicular to the A-A'. 2 (a) and (a ') form a field oxide film 201 on a P-type sub (for example, P-type substrate or P well) 200, and the substrate between the field oxide films 201 is P-type. This is a manufacturing process diagram in which a gate oxide film 202, a polysilicon film 203, and a tungsten silicide film 204 are sequentially formed after being doped with impurities. At this time, the thickness of the polysilicon film 203 may be 1000 kPa, and the thickness of the tungsten silicide film 204 may be 2000 kPa. In addition, the polysilicon layer 203 may be doped with a dockle in order to increase electrical conductivity. 2 (b) and (b ') show a limited etching of the tungsten silicide layer 204 and the polysilicon layer 203 by photolithography to form a gate electrode of a transistor, and form an n-source / drain region. To do this, ion implantation (e.g., phosphorous (dosage) of 1.6 × E13 ions / cm 2 and energy of 60KV) is applied to the entire surface of the substrate, followed by deposition of an insulating film to form a lightly doped drain (LDD) structure. And forming an spacer 205 through an etch back process and implanting ions (e.g., arsenic) with a dose of 5 × E15 ions / cm 2 and 40 KeV to form an n + source / drain region. Is a manufacturing process diagram in which n ⁺ source / drain regions 206 are formed by implanting with energy. At this time, as shown in the first (a) and the second (b '), the extended line of the gate electrode is operated as a word line. FIGS. 2 (c) and (c ') expose the memory cell transistors in which data is to be written using the photosensitive film 207 on the entire surface of the substrate, and implant ions into the channel region through the gate electrode of the memory cell transistor. It is a process chart. At this time, the ion-implanted memory cell transistor is switched from an increased type to a depleted type. As an example of the ion implantation, phosphorus (phosphorus) has a dose of 5 × E12-1 × E13 ions / ㎠ and an energy of 300-400 KeV. It can also be carried out. 2 (d) and (d ') show a bit line connected to a predetermined active region on a substrate through a contact hole after forming the HTO film 208 and the interlayer insulating film 209 after removing the photosensitive film 207. After forming 210, a protective film 411 is formed to complete the manufacturing process diagram. The interlayer insulating film 209 is typically formed by depositing a BPSG film and reflowing, wherein the ions implanted to form the n ⁺ source / drain region are driven and drive-in. The bit line 210 is formed of a metal (for example, aluminum) or the like, and the contact hole forming process is not shown in FIG. 2, but after forming the interlayer insulating layer 209, the contact hole is formed and aluminum is deposited. Patterning-etching results in bitline 210.

However, in the above manufacturing process, due to various causes (for example, poor in-plane uniformity of gate electrode forming films, foreign matters generated during the process, and poor ion implantation), the memory to be converted into a depletion type, that is, a depletion type memory The defects in which the cell transistors are not switched to the depletion type or the defects in which each word line or each bit line is bridged and shorted to each other occur.

In order to remedy defective cells caused by defects in the manufacturing process in such a mask ROM, a method of alternatively writing data using a redundant cell array or an error correcting code (abbreviated ECC circuit) is conventionally used. Methods and the like have been used. An example of a method using a redundancy cell array is disclosed by TOSHIBA, Japan, in 1989 on the IEEE International Solid State Circuits Conference (ISSCC) pages 128-129. An example of a method using an ECC circuit is Hitachi, Japan. 1983, ISSCC, pages 158-159, published by HITACHI.

3 is a functional block diagram of a mask ROM having a redundant cell array according to the prior art. The mask ROM shown in FIG. 3 has a memory cell array 300 divided into four and a redundancy cell array 310 used for defect relief. The row decoder 103 connected to one of four memory cell arrays by a row pre-decorder 302 for inputting an externally applied row address through the row address buffer 301. ), A word line is selected, and the column decoder 305 for inputting an externally applied column address through the column address buffer 304 and the column selector 306 connected to the column decoder 305. The bit line is selected by this. Accordingly, data of a specific memory cell selected by the decoding signal of the low address and the column address is loaded on the bit line, and the data is sensed by the sensor amplifier 308 through the bit selector gate 307. When a failure occurs at a specific address of the memory cell array, the defective address is stored in the fuse address decoder 311, and the data of all the memory cells connected to the word line where the defective cell is generated is redundant. Remember). Therefore, when the external address designates an address where a bad address occurs during the data read operation, the fuse address decoder 311 generates the spare row decoder 312 and the memory cell when the memory cell array fails or reads the address data. The bit selector 313 is operated. The spare column selector 314 and the spare row decoder 312 select spare bit lines and spare word lines of the redundant cell array, respectively. In this case, the bit selector 313 turns off the bit selector gate 307 connecting the memory cell array 300 and the sensor amplifier 308, and the redundancy cell array 310 and the sensor amplifier 308. ) Turns on the bit selector gate 309 for connecting < RTI ID = 0.0 > Therefore, the sensor amplifier 308 detects the data of the defective redundancy cell array.

4 is a partial circuit diagram of the redundancy cell array 310. The redundancy cell of FIG. 4 is an electrically blown polysilicon fuse cell. When data is written to the cell, the t1 and t2 signals are set low. At this time, when the output of the noah gate 400 selected by the fuse address becomes high, the pass transistor 401 is turned on, and one terminal of the polysilicon fuse 400 is connected to the ground terminal. At this time, when an external voltage of a predetermined size is applied to the voltage pad Vexi 403, the fuse 400 is blown to complete the write operation. In addition, when the data of the cell is read out, the t3 and t4 signals become 'high'. In this case, the noble gate 405 is turned off, and the applied voltage Vexi 403 is connected to the ground terminal by the ground terminal fast transistor 404. Therefore, the state (especially, stored data) of the fuse 400 blown by the spare word line and the spare bit line is read.

However, since the memory cell forming the redundancy cell array is composed of two transistors and one polysilicon fuse cell in the related art, an area thereof is increased compared to a memory cell array having a memory cell consisting of one transistor. . Therefore, in order to rescue a large number of defective cells, a large area of redundancy cell array is required, which is not effective. In addition, incorporating the ECC circuit as another method for the defect remedy has the disadvantage of increasing the chip size and delaying the access time.

Accordingly, an object of the present invention for solving the above problems is to provide a defect relief method of the mask rom which can repair defective cells without increasing the chip area.

Another object of the present invention is to provide a mask ROM defect repair method that can immediately correct a defect without using a separate defect repair circuit.

According to an aspect of the present invention, a plurality of memory cell transistors are formed on a semiconductor substrate and are formed of a plurality of active regions separated from each other by a channel region, and a gate electrode spaced apart from an upper surface of the channel region and a gate insulating film, and the memory. An interlayer insulating film extending over cell transistors and a protective film layer over the cell transistors, wherein a defect is generated during a data writing process in a data write defect relief method of a mask ROM for writing data by implanting ions into the channel region. A first step of locating a cell transistor, a second step of forming an ion implantation opening by restricting etching of an upper passivation layer of the defective memory cell transistor, and implanting ions through the opening to inject data into the channel region After the recording is made of a third process of forming a protective film layer It shall be.

In addition, the present invention for achieving the above object is a defect relief method of a read-only memory device having a plurality of memory cells in a matrix consisting of a word line and a bit line, and a protective film extending over the word line and the bit line. A first process of finding a site in which a short circuit occurs between a word line or a bit line and a defect has occurred, and a second process of limiting etching of the passivation layer on the shorted site to expose the short circuited site. And a third process of forming a protective film after the lines are separated from each other by etching the shorted portions of the liver.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

5 is a manufacturing process diagram showing a data recording defect repair method according to an embodiment of the present invention. (A)-(c) of FIG. 5 is sectional drawing cut along the AA 'of FIG. 1, and (a')-(c ') are the B-B' which is orthogonal to A-A '. It is a cross-section cut along. 5 (a) and 5 (a ') show the location of the defective cell after testing EDS (Electrical Die Sorting) with the mask rom which has undergone the manufacturing process of FIG. 5 (a) and 5 (a ') show that the second memory cell M2, which should be converted to the depletion type among the three memory cell transistors M1 to M3, still remains in an increased form due to a failure in the data writing process. There is a bad state. 5 (b) and 5 (b '), the protective film 211 is removed, and then the photoresist film 501 is formed on the entire surface of the substrate, and then the M2 memory cell transistor using an electron beam lithograpy technique. It is a manufacturing process diagram which converts into a depletion transistor by performing ion implantation after exposing only a site | part. Here, the EDS may be carried out before the protective film forming step, and the defective cells may be saved without removing the protective film 211. At this time, since the implanted ions must reach the channel region through the thick interlayer insulating film 209, the ions must be implanted with a high energy of at least 500 KeV. As an example of such an ion implantation process, phosphorus, which is a pentavalent ion, is injected at a dose of 7 × E12 to 1 × E13 ions / cm 2 and an energy of 850 to 900 KeV, followed by annealing at 500 ° C. May be performed. 5C is a manufacturing process diagram in which the protective film 502 is formed again to complete the defect repair process.

In the embodiment of FIG. 5, a description has been given of a data writing defect repair method in which a memory cell is first fabricated as an incremental transistor and converted into a depletion transistor at the time of data writing, but vice versa. The invention is established. That is, all those skilled in the art that the present invention can also be applied to the relief of data write defects in the case where the fabrication of the first memory cell is manufactured by the depletion transistor and the data recording is converted into the incremental transistor are all available. You will know. At this time, since trivalent ions (for example, boron ions) are implanted to record data, the ion implantation energy is lower than that of the embodiment of FIG. 5 which uses 5 ions for ion implantation at the time of defect relief. This allows for defect repair.

6 is a manufacturing process chart showing another embodiment of the data recording defect repair method according to the present invention. 6 (a) and 6 (a ') are the same as the above-mentioned 5 (a) and (a'), respectively. 6 (b) and 6 (b ') show that after removing the protective film 211, a photoresist film is formed on the entire surface of the substrate, and then only the M2 memory cell transistor region is exposed using an electron beam lithograpy technique. After that, the interlayer oxide film 209 and the HTO film 208 are sequentially etched to expose the upper surface of the gate electrode (tungsten silicide film 204), followed by ion implantation to convert into a depletion transistor. As a result, the fifth layer (b) can also implant ions with lower energy than this process, in which the interlayer insulating film 209 that remains unetched acts as an ion implantation mask and is a phosphate that is a pentavalent ion. The defects may be repaired by annealing with a dosing amount of 7 × E12 to 1 × E13 ions / cm 2 and an energy of 350 to 400 KeV, followed by annealing at 500 ° C. FIG. The protective film 602 is formed again to correct defects Jung is a manufacturing process chart is completed.

FIG. 7 is a manufacturing process diagram showing a defect repair method in the case of a failure in which a word line or a bit line is shorted as a second embodiment according to the present invention. FIG. 7 is a cross-sectional view taken along the line AA ′ of FIG. 1 (a) and is a cross-sectional view of a mask rom formed through the process of FIG. FIG. 7 (a) shows the site where the defective short of the word line is generated through the EDS test. Due to a short circuit between the word lines, the gate electrodes of the memory cells Ma and Mb are short-circuited with each other, so that an active region between the memory cells Ma and Mb is not formed. In FIG. 7 (b), after the upper protective layer 211 is etched away, the photoresist layer is formed on the entire surface of the substrate, and then the etch opening 702 is formed by only exposing the upper portion of the word line short-circuited using electron beam lithography. It is a manufacturing process chart. 7C shows that the interlayer insulating film 209, the HTO film 209, the tungsten silicide film 204, and the polysilicon film 203 are sequentially etched through the etching opening 702, and then the memory cells Ma and Mb are etched. It is a manufacturing process chart which performs ion implantation in order to form n ⁺ active area | region on the board | substrate between. FIG. 7D is a manufacturing process diagram in which the insulating film 703 is formed to a predetermined thickness to insulate the memory cells Ma and Mb, and then the protective film 704 is formed again to complete the defect relief. Therefore, the memory cells Ma and Mb are separated from each other to operate as respective memory cells, and the two memory cells are electrically connected to each other through the newly formed n ⁺ active region.

FIG. 8 is a manufacturing process diagram showing a defect repair method in a case where a defect occurs due to a short circuit between bit lines as another embodiment of the second embodiment according to the present invention. FIG. 7 is a cross-sectional view taken along the line BB ′ of FIG. 1A, and is a cross-sectional view of a mask rom formed through the process of FIG. 2. FIG. 8 (a) shows an area where a defect occurs due to a short circuit of a bit line through an EDS test. The bit lines 210a and 210b are shorted to each other due to a short circuit between the bit lines. 8B is a manufacturing process diagram in which the upper protective film 211 is etched away, the photosensitive film is formed on the entire surface of the substrate, and the etching opening is formed by only exposing the shorted portions between the bit lines using electron beam lithography. 8 (c) is a manufacturing process diagram in which the short-circuit bit line 210 is etched through the etching opening, and then a protective film 802 is formed to complete defect repair. Accordingly, the bit lines 210a and 210b operate as respective bit lines separated from each other.

In FIGS. 5 to 8, which are embodiments of the present invention, defect relief is carried out using electron beam lithography, but it has been found that the same effect can be obtained by using ion beam lithography instead of electron beam lithography. Anyone who knows will know.

As described above, the mask ROM defect repair method according to the present invention does not use a separate redundancy cell array, and directly exposes the defective cell region by using an electron beam lithography technique or an ion beam lithography technique to record data. In the case of a defect caused by a defect, ion implantation is performed to perform a defect repair. In the case of a defect caused by a short circuit between word lines or bit lines, the defects are removed by etching the shorted portions and performing defect repair. In order to adopt the redundancy cell or ECC circuit for defect repair, the problem that the area of the chip is increased is eliminated, and the number of bits to be repaired is not limited. Therefore, it provides a large yield improvement in terms of yield.

Claims (7)

A plurality of memory cell transistors formed on a semiconductor substrate and separated from each other in a channel region, a plurality of memory cell transistors formed on the channel region and a gate electrode spaced apart from the gate insulating layer, and an interlayer insulating layer extending over the memory cell transistors. And a protective film layer formed thereon, the method for resolving a data write defect of a read-only memory device which writes data by implanting ions into the channel region, wherein the location of a defective memory cell transistor during the data writing process is found. A first step, and a second step of forming an ion implantation opening by restricting etching the upper passivation layer of the defective memory cell transistor, and implanting ions through the opening to record data in the channel region, and then forming the passivation layer Read-only memory, characterized in that the third step of forming How to remedy data record defects in the device The method of claim 1, wherein after forming the photoresist film on the front surface of the second process, the photoresist film is removed by using an electron-beam lithography technique or an ion beam lithography technique to form an etch opening. And etching the passivation layer to form an ion implantation opening. The method of claim 1, wherein after forming the photoresist film on the front surface of the second tablet, the photoresist layer is removed by using an electron-beam lithography technique or an ion beam lithography technique to form an etch opening. And a second step of forming an opening for ion implantation by sequentially etching the passivation layer and the interlayer insulating layer to expose a top surface of the gate electrode. The method of claim 1 or 2, wherein the ion implantation is performed at an energy of 500 Kev or more. The method of claim 1, wherein the implanted ions are trivalent ions or pentavalent ions. In a defect remedy method of a read-only memory device having a plurality of memory cells in a matrix consisting of word lines and bit lines, and a protective film extending over the word lines and bit lines, a short circuit between word lines or between bit lines. And a second step of finding a site in which a defect has occurred and a second step of exposing a shorted portion by defining a protective layer on the upper portion of the shorted portion, and etching a shorted portion between the lines. And a third step of forming a protective film after the separation is performed. The method of claim 6, wherein after forming the photoresist film on the front surface of the second pin of the second step, the photoresist film is removed by using an electron-beam lithography technique or an ion beam lithography technique to form an etch opening. And etching the passivation layer through the second step of exposing the shorted portion.