KR960009623A - Phase-locked loop frequency synthesizer circuit - Google Patents

Phase-locked loop frequency synthesizer circuit Download PDF

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Publication number
KR960009623A
KR960009623A KR1019940019576A KR19940019576A KR960009623A KR 960009623 A KR960009623 A KR 960009623A KR 1019940019576 A KR1019940019576 A KR 1019940019576A KR 19940019576 A KR19940019576 A KR 19940019576A KR 960009623 A KR960009623 A KR 960009623A
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KR
South Korea
Prior art keywords
signal
phase
divider
phase error
output signal
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KR1019940019576A
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Korean (ko)
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KR100195086B1 (en
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박홍기
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김광호
삼성전자 주식회사
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Priority to KR1019940019576A priority Critical patent/KR100195086B1/en
Publication of KR960009623A publication Critical patent/KR960009623A/en
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Publication of KR100195086B1 publication Critical patent/KR100195086B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/199—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

초기 위상 에러를 검출하고 검출된 위상 에러가 크면 PLL의 루프 특성에 관계없이 위상 에러가 제로가 되도록 한다음 PLL 루프가 동작하도록 하는 PLL 주파수 신서사이저 회로가 개시되는 바, 이는 외부에서 공급되는 입력신호와 분주기의 출력신호의 위상을 비교하여 위상 에러에 비례하는 신호를 출력하는 위상 비교기와, 상기 위상 비교기의 출력을 DC 값으로 변환하여 주파수 제어신호로서 출력하는 루프 필터와, 상기 루프 필터에서 출력되는 주파수 제어신호에 따라 발진 주파수가 가변되는 전압 제어 발진기와, 상기 전압 제어 발진기의 출력신호를 1/N로 분주하여 위상 비교기에 공급하는 분주기와, 상기 위상 비교기로 입력되는 입력신호와 분주기의 출력신호의 초기 위상 에러가 큰 경우에 상기 분주기를 리셋시켜 순간적으로 상기 위상 비교기로 입력되는 입력신호와 분주기의 출력신호의 위상을 같게 하는 신호 발생부로 구성되어, 위상 비교기에 공급되는 두 입력신호의 위상 에러를 검출하여 이 위상 에러가 크게 될 경우에는 분주기를 리셋시켜 PLL의 루프 동작 특성에 관계없이 분주기의 출력신호를 입력신호의 위상과 순간적으로 같아지도록 한 다음에 PLL 루프가 정상동작 하도록 하여 초기 위상 에러를 없앰으로써, 초기 위상 에러에 비례하는 풀-인 타임을 짧게 하여 응답속도를 빠르게 한다.A PLL frequency synthesizer circuit is disclosed which detects an initial phase error and causes a phase error to be zero regardless of the loop characteristics of the PLL if the detected phase error is large, and then causes the PLL loop to operate. A phase comparator for comparing a phase of an output signal of a divider and outputting a signal proportional to a phase error, a loop filter for converting an output of the phase comparator to a DC value and outputting the signal as a frequency control signal, and outputting from the loop filter A voltage controlled oscillator having an oscillation frequency variable according to a frequency control signal, a divider for dividing an output signal of the voltage controlled oscillator at 1 / N and supplying it to a phase comparator, and an input signal and a divider inputted to the phase comparator When the initial phase error of the output signal is large, the frequency divider is reset to instantaneously enter the phase comparator. It consists of a signal generator that equalizes the output signal of the input signal and the output signal of the divider, and detects the phase error of the two input signals supplied to the phase comparator and resets the divider when the phase error becomes large. Regardless of the loop operation characteristics, the output signal of the divider is instantaneously equal to the phase of the input signal, and then the PLL loop operates normally to eliminate the initial phase error, thereby reducing the pull-in time proportional to the initial phase error. To speed up the response.

Description

위상동기 루프 주파수 신서사이저 회로Phase-locked loop frequency synthesizer circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 이 발명에 따른 PLL 주파수 신서사이저 회로의 블럭도.2 is a block diagram of a PLL frequency synthesizer circuit according to the present invention.

제3도의 (a),(b)는 상기 제2도의 각 부의 동작 파형도이다.(A), (b) of FIG. 3 is an operation waveform diagram of each part of the said FIG.

Claims (2)

외부에서 공급되는 입력 신호와 분주기의 출력신호의 위상을 비교하여 위상 에러에 비례하는 신호를 출력하는 위상 비교기와, 상기 위상 비교기의 출력을 DC값으로 변환하여 주파수 제어신호로서 출력하는 루프 필터와, 상기 루프 필터에서 출력되는 주파수 제어 신호에 따라 발진 주파수가 가변되는 전압 제어 발진기와, 상기 전압 제어 발진기의 출력신호를 1/N로 분주하여 위상 비교기에 공급하는 분주기로 구성되는 위상 동기 루프 주파수 신서사이저 회로에 있어서, 상기 위상 비교기로 입력되는 입력 신호와 분주기의 출력신호의 위상 에러가 크면 상기 분주기를 리셋시켜 순간적으로 상기 위상 비교기로 입력되는 입력신호와 분주기의 출력신호의 위상을 같게 하는 신호 발생 수단이 구비되는 위상동기 루프 주파수 신서사이저 회로.A phase comparator for comparing a phase of an externally supplied input signal and a divider output signal and outputting a signal proportional to a phase error, a loop filter for converting the output of the phase comparator to a DC value and outputting it as a frequency control signal; A phase locked loop frequency synthesizer comprising a voltage controlled oscillator whose oscillation frequency is varied according to a frequency control signal output from the loop filter, and a divider for dividing an output signal of the voltage controlled oscillator at 1 / N and supplying it to a phase comparator In the circuit, if the phase error of the input signal input to the phase comparator and the output signal of the divider is large, the divider is reset so that the phase of the input signal input to the phase comparator and the output signal of the divider are instantaneously equal. A phase locked loop frequency synthesizer circuit provided with signal generating means. 제1항에 있어서, 상기 신호 발생 수단은, 상기 분주기의 출력신호가 'H'에서 'L'로 변환하는 곳에서 제1 제어신호를 출력하는 제1신호 발생부와, 외부에서 공급되는 입력신호가 'H'에서 'L'로 변환하고 동시에 제1제어신호가 'L'인 기간에서만 제2 제어신호를 분주기로 출력하여 분주기를 리셋시키는 제2신호 발생부로 구성되는 위상동기 루프 주파수 신서사이저 회로.The apparatus of claim 1, wherein the signal generator comprises: a first signal generator for outputting a first control signal where the output signal of the frequency divider is converted from 'H' to 'L', and an input supplied externally Phase-synchronized loop frequency synthesizer comprising a second signal generator for converting the signal from 'H' to 'L' and simultaneously outputting the second control signal to the divider only when the first control signal is 'L'. Circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940019576A 1994-08-09 1994-08-09 Synthesizer circuit of phase locked loop frequency KR100195086B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940019576A KR100195086B1 (en) 1994-08-09 1994-08-09 Synthesizer circuit of phase locked loop frequency

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940019576A KR100195086B1 (en) 1994-08-09 1994-08-09 Synthesizer circuit of phase locked loop frequency

Publications (2)

Publication Number Publication Date
KR960009623A true KR960009623A (en) 1996-03-22
KR100195086B1 KR100195086B1 (en) 1999-06-15

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KR1019940019576A KR100195086B1 (en) 1994-08-09 1994-08-09 Synthesizer circuit of phase locked loop frequency

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KR100195086B1 (en) 1999-06-15

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