KR960009493A - D channel controller - Google Patents

D channel controller Download PDF

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Publication number
KR960009493A
KR960009493A KR1019940021614A KR19940021614A KR960009493A KR 960009493 A KR960009493 A KR 960009493A KR 1019940021614 A KR1019940021614 A KR 1019940021614A KR 19940021614 A KR19940021614 A KR 19940021614A KR 960009493 A KR960009493 A KR 960009493A
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South Korea
Prior art keywords
clock
channel
data
isdn
central processing
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KR1019940021614A
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Korean (ko)
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KR970009695B1 (en
Inventor
이재철
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구자홍
엘지전자 주식회사
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Priority to KR1019940021614A priority Critical patent/KR970009695B1/en
Publication of KR960009493A publication Critical patent/KR960009493A/en
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Publication of KR970009695B1 publication Critical patent/KR970009695B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Communication Control (AREA)

Abstract

본 발명은 ISON 에서의 D채널 제어장치에 관한 것으로서, 다양한 속도의 D채널의 액세스 및 다중화된 ISDN 채널에서 HDLC기능을 위한 전용칩이 필요없이 중앙처리장치에서 D채널 데이타민을 검출하여 직접 제어하도록 한 것이다.The present invention relates to a D-channel control device in ISON, to detect and directly control the D-channel datamin in the central processing unit without the need for a dedicated chip for accessing the D-channel at various speeds and the HDLC function in the multiplexed ISDN channel. It is.

종래에는 B,D채널의 제어를 위해 HDLC전용칩을 사용하므로서 회로가 복잡해지는 문제점을 개선코자 클럭발생회로에 의해 다중화된 ISCN의 직렬 프레임에서 D채널동안만의 시간을 검출하여 중앙처리장치에 클럭을 공급하여 D채널의 직렬데이타를 중앙처리장치에 입력하거나 중앙처리장치에서 출력하는 게이팅 클럭에 의한 ISDN에서의 D채널 데이타를 엑세스화도록 한 것이다.In order to improve the complexity of the circuit by using a dedicated HDLC chip for controlling the B and D channels, the clock is detected in the central processing unit by detecting the time during the D channel only in the serial frame of the ISCN multiplexed by the clock generation circuit. The D-channel serial data of the D-channel is inputted to the central processing unit or the D-channel data of the ISDN by the gating clock outputted from the central processing unit is accessed.

Description

디(D)채널 제어장치D channel controller

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명 D채널 제어장치의 블럭 구성도.2 is a block diagram of a D-channel controller of the present invention.

Claims (2)

ISDN망과 연결되어 음성, 제어 및 동기 데이타와 동기클럭등을 츨력하기 위한 ISDN 접속수단을 통해 D채널 시간동안 입력되는 데이타를 HDLC방식으로 처리하는 중앙처리장치와, 상기 ISDN 접속수단의 직렬 데이타 및 시스템 하이웨이로부터의 데이타를 다중화 및 역다중화(MUX/DEMUX)하는 다중화/역다중화 수단과, 상기 ISDN 접속수단으로부터 검출한 동기클럭(CLK)과 프레임 신호(Frame)에 의해 D채널 시간동안만 제1,제2게이팅(gating1,2)클럭을 발생하는 클럭 발생수단과, 상기 클럭 발생수단으로부터 출력된 게이팅 클럭에 따라 상기 중앙처리장치와 상기 다중화/역다중화 수단으로부터 상기 ISDN 접속수단으로 전송되는 데이타를 제어하여 상호간의 충돌을 방지하는 데이타 충돌 방지수단을 포함하여 구성된 것을 특징으로 하는 D채널 제어장치.A central processing unit (HDLC) for processing data input during D-channel time through an ISDN access unit connected to an ISDN network for outputting voice, control and synchronization data and a synchronization clock; and serial data of the ISDN connection unit. A multiplexing / demultiplexing means for multiplexing and demultiplexing (MUX / DEMUX) data from a system highway, and a synchronization clock (CLK) and a frame signal (Frame) detected from the ISDN access means for the first D-channel time only. Clock transmission means for generating a second gating clock; and data transmitted from the CPU and the multiplexing / demultiplexing means to the ISDN access means according to a gating clock output from the clock generating means. D-channel control device comprising a data collision prevention means for controlling the collision to prevent mutual collision. 제 1항에 있어서, 상기 데이타 충돌 방지수단은 상기 ISDN 접속수단으로 송신하는 상기 중앙처리장치와 상기 다중화/역다중화 수단으로부터 송신되는 데이타의 흐름을 제어하여 데이타 충돌을 방지하는 제1,제2의 3상태 버퍼와, 상기 클럭 발생수단으로부터 얻어진 제2게이팅 클럭(Gating2)을 반전시켜 상기 제1의 3상태 버퍼를 제어하는 제1인버터와, 상기 클럭 발생수단으로부터 출력된 제1게이팅 클럭(Gating1)을 반전시키는 제2인버터와, 상기 제2인버터로부터 출력된 클럭의 제어에 따라 상기 ISDN 접속수단에서 중앙처리장치의 클럭(CLK)전송을 제어하는 제3의 3상태 버퍼로 구성됨을 특징으로 하는 D채널 제어장치.2. The apparatus of claim 1, wherein the data collision prevention means controls the flow of data transmitted from the CPU and the multiplexing / demultiplexing means to the ISDN access means to prevent data collisions. A first inverter controlling the first tri-state buffer by inverting the tri-state buffer, the second gating clock Gating2 obtained from the clock generating means, and the first gating clock Gating1 output from the clock generating means. And a third three-state buffer for controlling the clock (CLK) transmission of the central processing unit by the ISDN access unit under the control of the clock output from the second inverter. Channel Control. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940021614A 1994-08-30 1994-08-30 Apparatus for controlling d-channel KR970009695B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940021614A KR970009695B1 (en) 1994-08-30 1994-08-30 Apparatus for controlling d-channel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940021614A KR970009695B1 (en) 1994-08-30 1994-08-30 Apparatus for controlling d-channel

Publications (2)

Publication Number Publication Date
KR960009493A true KR960009493A (en) 1996-03-22
KR970009695B1 KR970009695B1 (en) 1997-06-17

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000074818A (en) * 1999-05-26 2000-12-15 정혜옥 A Composition for Preserving Rice and Method for preparing the same
KR20020022241A (en) * 2000-09-19 2002-03-27 김상진 damp proof manufacture method of producing for mixing corn

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000074818A (en) * 1999-05-26 2000-12-15 정혜옥 A Composition for Preserving Rice and Method for preparing the same
KR20020022241A (en) * 2000-09-19 2002-03-27 김상진 damp proof manufacture method of producing for mixing corn

Also Published As

Publication number Publication date
KR970009695B1 (en) 1997-06-17

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