KR960008903B1 - Forming method of insulating film on the semiconductor substrate - Google Patents
Forming method of insulating film on the semiconductor substrate Download PDFInfo
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- KR960008903B1 KR960008903B1 KR1019920025009A KR920025009A KR960008903B1 KR 960008903 B1 KR960008903 B1 KR 960008903B1 KR 1019920025009 A KR1019920025009 A KR 1019920025009A KR 920025009 A KR920025009 A KR 920025009A KR 960008903 B1 KR960008903 B1 KR 960008903B1
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- Prior art keywords
- dielectric film
- gas
- film
- forming
- semiconductor substrate
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 title claims abstract description 14
- 239000004065 semiconductor Substances 0.000 title claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 125000001153 fluoro group Chemical group F* 0.000 claims abstract description 8
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 6
- 239000011737 fluorine Substances 0.000 claims abstract description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 10
- 239000010453 quartz Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 abstract description 2
- 238000000137 annealing Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 30
- 125000004429 atom Chemical group 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000000460 chlorine Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 229910052783 alkali metal Inorganic materials 0.000 description 1
- 150000001340 alkali metals Chemical class 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
제1도는 종래의 유전체막의 제조방법을 예시하는 단면도.1 is a cross-sectional view illustrating a conventional method for producing a dielectric film.
제2a~b도는 본 발명의 일 실시예에 따른 유전체막의 제조공정을 보인 단면도.2A to 2B are cross-sectional views illustrating a process of manufacturing a dielectric film according to an embodiment of the present invention.
제3a~c도는 본 발명의 다른 실시예에 따른 유전체막의 제조공정을 보인 단면도.3A to 3C are cross-sectional views illustrating a process of manufacturing a dielectric film according to another embodiment of the present invention.
본 발명은 반도체 기판상에 유전체막을 형성하는 방법에 관한 것으로서, 특히 기판과 유전체막 사이의 계면 불소가 주입되게 하는 유전체막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a dielectric film on a semiconductor substrate, and more particularly to a method of forming a dielectric film in which interfacial fluorine is injected between a substrate and a dielectric film.
종래의 유전체막 형성기술은 O2가스막으로 도입하여 실리콘을 산화시키는 건식산화법과, 게더링 효과(gettering effect)를 위하여 산화막(SiO2막)을 형성할 때 계속하여 HCl 가스 등을 사용하는 방법이 이용되고 있다.Conventional dielectric film formation techniques include a dry oxidation method for introducing silicon into an O 2 gas film and oxidizing silicon, and a method of continuously using HCl gas or the like when forming an oxide film (SiO 2 film) for a gettering effect. It is used.
그런데 이 방법으로서는 유전체막중에 염소(Cl)원자가 과다하게 함유되어 박막의 질을 떨어뜨리는 문제점이 있다. 종래의 유전체막 형성기술을 반도체 소자의 제조에 사용하면 유전체막에 핀홀(pin-hole)등의 결함이 발생하기도 하고, 또한 알카리 이온의 충분히 제거되지도 않을 뿐만 아니라 계면준위 밀도도 충분히 작게 억제되지 않는 등의 문제점이 발생한다.However, this method has a problem in that the chlorine (Cl) atoms are excessively contained in the dielectric film, thereby degrading the quality of the thin film. When the conventional dielectric film forming technique is used in the manufacture of semiconductor devices, defects such as pin-holes may occur in the dielectric film, and not only the alkali ions may be sufficiently removed but also the interfacial level density is not sufficiently suppressed. Problems occur.
제1도는 상기의 방법으로 기판(1) 상에 SiO2막(2)과 다결정 실리콘층(3)을 차례로 형성한 상태의 단면도이다.1 is a cross-sectional view of a state in which a SiO 2 film 2 and a polycrystalline silicon layer 3 are sequentially formed on a substrate 1 by the above method.
본 발명은 이러한 제반 문제점들을 해소하는 유전체막의 형성방법을 제공하는데 그 목적이 있다.It is an object of the present invention to provide a method for forming a dielectric film that solves these problems.
이하, 첨부도면에 의거하여 본 발명의 실시예를 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
본 발명은, 제2a도에 나타낸 바와 같이, 실리콘 웨이퍼(Si wafer)(1)를 석영관로에 넣어 산화 온도 900℃에서 O2가스를 도입하여 10nm정도의 두께의 산화막(2)을 형성할때, 산화과정의 마지막 3~5분간에만 제2b도와 같이 F2가스를 석영관 내에 도입하면 SiO2/Si의 계면에 블소가 도입되기 때문에 실리콘웨이퍼(1) 표면에 Na등의 알카리 금속의 혼입과 핀홀 등이 없고, 또한 계면준위 밀도가 충분히 작아지는 유전체막(2)이 생성될 수 있다.As shown in FIG. 2A, when the silicon wafer 1 is placed in a quartz tube, O 2 gas is introduced at an oxidation temperature of 900 ° C. to form an oxide film 2 having a thickness of about 10 nm. When the F 2 gas is introduced into the quartz tube only in the last 3 ~ 5 minutes of the oxidation process, the bloso is introduced at the interface of SiO 2 / Si, so that alkali metal such as Na is mixed on the surface of the silicon wafer (1). The dielectric film 2 can be formed without pinholes or the like and with sufficiently low interface density.
이렇게 생성된 유전체막(2)과 Si기판(1) 계면에는 1012개/cm2정도의 불소원자가 축적(pile-up)되어 계면준위 밀도가 1010개/cm2·eV이하로 감소된다.At the interface between the dielectric film 2 and the Si substrate 1 thus produced, fluorine atoms of about 10 12 atoms / cm 2 are piled up to reduce the interface density to 10 10 atoms / cm 2 or less.
또한, F2가스대신에 HF 가스를 사용하여도 같은 효과가 나타나며 O2가스 대신에 O3가스를 사용해도 바람직한 효과를 기대할 수 있다.In addition, the same effect is obtained when HF gas is used instead of F 2 gas, and a desirable effect can be expected even when O 3 gas is used instead of O 2 gas.
유전체막중 Si3N4막을 생성할 경우에는 F2가스, ,혹은 HF 가스와 NH3가스와의 혼합 가스를 흘리면 핀홀이 없고 계면준위 밀도가 충분히 작은 유전체막을 형성할 수 있다. 또한 NH3가스 대신에 NO2가스를 사용해도 좋은 효과가 있다.When the Si 3 N 4 film is formed in the dielectric film, a dielectric film having no pinhole and sufficiently low interfacial density can be formed by flowing F 2 gas, or a mixed gas of HF gas and NH 3 gas. In addition, it is also possible to use the NO 2 gas in place of the NH 3 gas.
또 SiO2막에 10keV로부터 25keV정도의 낮은 가속 에너지로 불소 이온을 1014~1015/cm2정도의 도즈(dose)량으로 주입시켜서 전술한 것과 동일하게 SiO2/Si 계면에 불소원자를 도입시킬 수 있다.In addition, fluorine atoms are introduced into the SiO 2 / Si interface at a dose of about 10 14 to 10 15 / cm 2 at a low acceleration energy of 10 keV to 25 keV in the SiO 2 film. You can.
불소이온 주입 후 900℃, 10분 정도로 열처리(thermal annealing)함으로써 불소원자가 SiO2/Si 계면에 축적되어 계면준위 밀도를 감소시키는 효과가 있다.By thermal annealing at 900 ° C. for 10 minutes after fluorine ion injection, fluorine atoms accumulate at the SiO 2 / Si interface, thereby reducing the interface density.
불소원자 주입 후 열처리 방법은 SiO2막이 아닌 Si3N4막 등의 유전체막에도 적용시킬 수 있고 유전체막의 두께가 30nm 이하에서도 적용이 가능하다.After the fluorine atom injection, the heat treatment method can be applied to dielectric films such as Si 3 N 4 films, not SiO 2 films, and can be applied even when the thickness of the dielectric films is 30 nm or less.
또한 본 발명의 다른 실시예를 보인 제3a도와 같이 실리콘 기판(1)상에 형성된 SiO2막(2)위에 30nm정도의 다결정 실리콘(poly-Si)막(3)을 성장시킨 후에, 제3b도와 같이 불소원자를 주입한 다음 제3c도와 같이 열확산(F-implantation-implantation -thermal diffusion)시킨다.In addition, after the polycrystalline silicon (poly-Si) film 3 of about 30 nm is grown on the SiO 2 film 2 formed on the silicon substrate 1, as shown in FIG. 3a showing another embodiment of the present invention, After injecting the fluorine atom as shown in Figure 3c it is thermal diffusion (F-implantation-implantation -thermal diffusion).
이때, SiO2/Si 기판의 계면에 불소원자가 축적되어 유전체막중의 결함 및 계면준위 밀도를 감소시키는 등의 효과가 생기기 때문에 유전체막의 질을 향상시킬 수 있다.At this time, since the fluorine atoms are accumulated at the interface of the SiO 2 / Si substrate to reduce the defects in the dielectric film and the density of the interface level, the quality of the dielectric film can be improved.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920025009A KR960008903B1 (en) | 1992-12-22 | 1992-12-22 | Forming method of insulating film on the semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920025009A KR960008903B1 (en) | 1992-12-22 | 1992-12-22 | Forming method of insulating film on the semiconductor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940016581A KR940016581A (en) | 1994-07-23 |
| KR960008903B1 true KR960008903B1 (en) | 1996-07-05 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920025009A KR960008903B1 (en) | 1992-12-22 | 1992-12-22 | Forming method of insulating film on the semiconductor substrate |
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| Country | Link |
|---|---|
| KR (1) | KR960008903B1 (en) |
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1992
- 1992-12-22 KR KR1019920025009A patent/KR960008903B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR940016581A (en) | 1994-07-23 |
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