KR960008676Y1 - Circuit for peaking r,g,or b chrominance signal - Google Patents
Circuit for peaking r,g,or b chrominance signal Download PDFInfo
- Publication number
- KR960008676Y1 KR960008676Y1 KR92023593U KR920023593U KR960008676Y1 KR 960008676 Y1 KR960008676 Y1 KR 960008676Y1 KR 92023593 U KR92023593 U KR 92023593U KR 920023593 U KR920023593 U KR 920023593U KR 960008676 Y1 KR960008676 Y1 KR 960008676Y1
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- South Korea
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- video signal
- circuit
- transistor
- resistor
- peaking
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
- H04N9/646—Circuits for processing colour signals for image enhancement, e.g. vertical detail restoration, cross-colour elimination, contour correction, chrominance trapping filters
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Processing Of Color Television Signals (AREA)
- Picture Signal Circuits (AREA)
Abstract
내용 없음.No content.
Description
제1도는 본 고안의 자동해상도 개선회로를 보인 회로도이다.1 is a circuit diagram showing an automatic resolution improvement circuit of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : R, G, B 영상신호 출력부 20 : 비디오 IC10: R, G, B video signal output unit 20: video IC
30 : 영상신호 검출부 40 : 브라운관30: video signal detection unit 40: CRT
Q1, Q2 : 트랜지스터 R1-R10 : 저항Q1, Q2: transistor R1-R10: resistor
C1, C2 : 콘덴서 L1 : 코일C1, C2: condenser L1: coil
본 고안은 R, G, B 영상신호를 최종으로 출력하는 것으로, 특히 외부(EXSTERNAL)영상신호 입력시 신호의 최종 영상신호에 피이킹(Peaking)을 시키므로서 해상도를 향상시키고자 한 자동해상도 개선회로에 관한 것이다.The present invention finally outputs the R, G, and B video signals. In particular, an automatic resolution improvement circuit is designed to improve the resolution by peaking the final video signal of the signal when the external video signal is input. It is about.
종래에는 해상도는 화상의 섬세한 부분이 어느 정도 세밀하게 재현되는지를 나타내는 정도를 말하며, 수직해상도와 수평해상도로 나누어 표시한다.In the related art, the resolution refers to the degree to which the fine parts of an image are reproduced in detail, and is divided into vertical resolution and horizontal resolution.
텔레비젼에서는 화면의 높이 사이에 같은 간격으로 번갈아 그은 후에 흑백 수평방향의 선을 몇개 까지 나타낼 수 있는 지로 수직해상도를 나타내며, 높이와 같은 길이사이에 번갈아 그은 흑백 수직방향에 선이 몇개가 재현되는 지로 수평해상도를 나타내어 왔었으므로 복잡한 회로로 구성되어 작업공정이 불편한 문제점이 있어왔다.In televisions, the vertical resolution is represented by the number of lines in the black and white horizontal direction alternately between the heights of the screens, and the horizontal resolution is represented by the number of lines reproduced in the vertical black and white direction alternately between the heights and lengths. Since the resolution has been shown, there is a problem that the work process is inconvenient because it is composed of a complex circuit.
본 고안은 상기와 같은 문제점을 해결하고자 안출한 것으로서 본 고안의 목적은 R, G, B 영상신호 출력단으로부터 영상신호 출력시에 브라운관에 연결된 버퍼회로에 피이킹을 주어 고역차단주파수 부근에서 이득의 저하를 막기 위한 바이패스 콘덴서를 이용함으로써 보다 높은 해상도를 출력시킬 수 있도록 한 자동해상도 개선회로를 제공하고자 하는 것이다.The present invention has been made to solve the above problems, and an object of the present invention is to give a peak to a buffer circuit connected to a CRT when outputting an image signal from an R, G, B image signal output stage, thereby reducing gain in the vicinity of a high-frequency cutoff frequency. The purpose of the present invention is to provide an automatic resolution improvement circuit capable of outputting a higher resolution by using a bypass capacitor to prevent circuit breakers.
상기와 같은 목적을 달성하기 위하여 본 고안의 제1도를 참조하여 구성을 설명하면 다음과 같다.Referring to FIG. 1 of the present invention in order to achieve the above object, the configuration is as follows.
영상신호 출력부(10)로부터 출력되는 영상신호가 비디오 IC(20)을 거쳐 드라이브저항(R10)과 컷오프 저항(R8)이 에미터단에 연결된 버퍼용 트랜지스터(Q2)를 거쳐 브라운관(40)에 연결되도록 한 통상의 영상신호 최종 출력회로에 있어서,The video signal outputted from the video signal output unit 10 is connected to the CRT via the video IC 20 through the buffer transistor Q2 connected to the drive resistor R10 and the cutoff resistor R8 at the emitter stage. In the normal video signal final output circuit,
영상신호 출력시에 하이 레벨의 신호를 출력할 수 있도록 구비된 상기의 영상신호 출력부(10)의 출력단자(P1)에 저항(R2)을 거쳐 트랜지스터(Q1)의 베이스에 연결하고 콜렉터측에 콘덴서(C1)와 저항(R1)을 직렬연결하여 트랜지스터(Q2)을 이미터 피이킹 시킬 수 있도록 노드점 A에 연결하여 구성된다.The output terminal P1 of the video signal output unit 10 provided to output a high level signal at the time of outputting the video signal is connected to the base of the transistor Q1 via a resistor R2 and connected to the collector side. The capacitor C1 and the resistor R1 are connected in series to connect the node point A to emit the transistor Q2.
상기의 구성을 토대로 본 고안의 상세한 동작설명은 다음과 같다.Detailed operation description of the present invention based on the above configuration is as follows.
영상신호는 비디오부(20)을 거쳐 트랜지스터(Q2)에 인가되고 저항(R5)과 코일(L1)이 병렬로 이루어진 필터를 거쳐 브라운관(40)으로 출력되며, R, G, B 영상신호 출력부(10)으로부터 출력되는 영상신호는 저항(R2)을 거쳐 트랜지스터(Q1)의 베이스로 입력되고, 상기의 R, G, B 영상신호 출력부(10)의 영상신호 출력단(P1)으로부터 출력되는 하이레벨의 신호는 저항(R2)을 거쳐 트랜지스터(Q1)의 베이스에 인가되어 트랜지스터(Q1)를 도통시키고 트랜지스터(Q1)의 에미터에 걸린 저항(R1)과 콘덴서(C1)가 그라운드로 동작되고 이는 이미터 피이킹이 되어 기조정된 콘덴서(C1)의 값에 따라 5-7MHz까지 해상도를 높일 수 있게 되는 것이다.The image signal is applied to the transistor Q2 via the video unit 20 and output to the CRT 40 through a filter in which the resistor R5 and the coil L1 are in parallel, and outputs the R, G, and B image signals. The video signal output from the (10) is input to the base of the transistor (Q1) via a resistor (R2), and the high output from the video signal output terminal (P1) of the R, G, B video signal output unit 10 described above. The signal of the level is applied to the base of transistor Q1 via resistor R2 to conduct transistor Q1, and resistor R1 and capacitor C1 at the emitter of transistor Q1 are operated to ground. Emitter peaking results in a resolution up to 5-7MHz, depending on the value of the pre-adjusted capacitor (C1).
이와 같이 본 고안을 간단하게 영상신호 검출부(30)을 영상신호 최종출력단에 연결하여 각 R, G, B 신호를 이미터피이킹시키므로서 시청자들에게 양질의 화면을 제공할 수 있게 되는 고안이다.As described above, the present invention is simply designed to connect the video signal detection unit 30 to the video signal final output terminal to emit a peak of each R, G, B signal, thereby providing a high-quality screen to viewers.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR92023593U KR960008676Y1 (en) | 1992-11-27 | 1992-11-27 | Circuit for peaking r,g,or b chrominance signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR92023593U KR960008676Y1 (en) | 1992-11-27 | 1992-11-27 | Circuit for peaking r,g,or b chrominance signal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940014051U KR940014051U (en) | 1994-06-29 |
| KR960008676Y1 true KR960008676Y1 (en) | 1996-10-07 |
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ID=19344953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR92023593U KR960008676Y1 (en) | 1992-11-27 | 1992-11-27 | Circuit for peaking r,g,or b chrominance signal |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR960008676Y1 (en) |
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1992
- 1992-11-27 KR KR92023593U patent/KR960008676Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR940014051U (en) | 1994-06-29 |
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