KR940008039B1 - Image signal output circuit of hi-vision - Google Patents

Image signal output circuit of hi-vision Download PDF

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Publication number
KR940008039B1
KR940008039B1 KR1019910020046A KR910020046A KR940008039B1 KR 940008039 B1 KR940008039 B1 KR 940008039B1 KR 1019910020046 A KR1019910020046 A KR 1019910020046A KR 910020046 A KR910020046 A KR 910020046A KR 940008039 B1 KR940008039 B1 KR 940008039B1
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KR
South Korea
Prior art keywords
transistor
vision
output circuit
signal output
base
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KR1019910020046A
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Korean (ko)
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KR930011645A (en
Inventor
김용성
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대우전자 주식회사
배순훈
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Priority to KR1019910020046A priority Critical patent/KR940008039B1/en
Publication of KR930011645A publication Critical patent/KR930011645A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/21—Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
    • H04N5/213—Circuitry for suppressing or minimising impulsive noise

Abstract

The image signal output circuit for high vision includes a DC level adjuster having first and second resistors receiving a horizontal deflection blanking signal, and a transistor having a base connected to the DC level adjuster and a collector connected to the base of another transistor, thereby eliminating screen noise.

Description

하이 -비젼(Hi-Vision)용 영상신호 출력회로Image Signal Output Circuit for Hi-Vision

제1도는 NTSC와 하이 비젼의 수평 동기신호 비교도표.1 is a diagram of the horizontal synchronization signal of NTSC and high vision.

제2도는 본 발명에 의한 영상신호 출력회로.2 is a video signal output circuit according to the present invention.

제3도는 제2도 각부의 파형 비교도표.3 is a waveform comparison chart of the parts of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1,1' : 영상 증폭회로 DCL : DC 레벨 조절부1,1 ': Video amplifier circuit DCL: DC level control unit

R2,R3: 저항 Ql,Q2: 트랜지스터R 2 , R 3 : Resistor Q l , Q 2 : Transistor

본 발명은 하이비젼에서 사용되는 비디오 신호 출력회로에 관한 것으로, 하이비젼 고유의 3치(3-Value)동기신호에 의한 영상잡음을 제거할 수 있도록 한 것이다.The present invention relates to a video signal output circuit used in high-vision, and to eliminate the image noise caused by the high-vision intrinsic 3-value synchronous signal.

현재 개발완료된 고화질 TV 방식중 하이비젼 신호는 동기신호가 정확하게 잡히도록 하기 위하여 제1도로 보인 바와같이 3가지 레벨로 구성되어 있다.Among the high-definition TV systems currently developed, the high-vision signal is composed of three levels as shown in FIG. 1 in order to accurately capture the synchronization signal.

그러므로 이러한 동기신호가 영상신호로서 증폭되고 출력되면 양(positive) 부분에 의하여 화면 노이즈가 생기게 되는 것이다.Therefore, when such a synchronization signal is amplified and output as a video signal, screen noise is generated by a positive portion.

본 발명은 이같은 화면 노이즈 발생의 원인이 되는 양부분의 동기신호 지속시간이 수평 브랭킹신호의 지속시간에 비하여 매우 짧으며 이러한 수평 브랭킹신호의 지속시간중에 하이비젼의 3치 동기신호에 의한 수평 동기신호 지속시간이 항상 포함된다는 점에 착안하여 수평 브랭킹신호의 지속시간 동안 영상신호 출력역시 3치 동기신호에 무관하게 음(Negative)상태가 되도록 함으로써 화면에 앙부분에 의한 노이즈가 나타나지 않도록 한 것으로, 이를 첨부된 도면에 따라 상세히 설명하면 다음과 같다.According to the present invention, the duration of the synchronization signal of both parts which causes the occurrence of such screen noise is very short compared to the duration of the horizontal blanking signal, and during the duration of the horizontal blanking signal, Taking into account that the sync signal duration is always included, the video signal output is also negative during the duration of the horizontal blanking signal so that the noise does not appear on the screen. When described in detail according to the accompanying drawings as follows.

공지된 영상 증폭회로(1)의 출력(out)에 트랜지스터(Q2)의 베이스를 접속하고 저항(Rl)이 접속된 에미터에 영상 증폭회로(1')의 입력(In)을 접속하여서 된 공지의 것에 있어서, 수평 편향 출력과 접속된 저항(R2)및 저항(R3)으로 DC 레벨 조절부(DCL)를 구성하고 이에 트랜지스터(Ql)의 베이스를 접속하며 그 콜렉터를 상기 트랜지스터(Q2)의 베이스와 연결하여서 된 것으로 미설명부호 Vcc는 전원이다.By connecting the base of the transistor Q 2 to the output (out) of the known image amplifying circuit 1, and connecting the input (In) of the image amplifying circuit 1 'to the emitter to which the resistor (R l ) is connected. In the known art, a DC level control unit (DCL) is formed by a resistor (R 2 ) and a resistor (R 3 ) connected with a horizontal deflection output, and the base of the transistor (Q 1 ) is connected thereto, and the collector is connected to the transistor. It is connected to the base of (Q 2 ). Unexplained code Vcc is power.

이와같이 된 본 발명은 세트의 작동시에 영상 증폭회로(1)로 부터 제3도(a)에 도시된 바와같은 파형이 입력되고 이는 중폭된 후 트랜지스터(Q2)의 베이스에 인가되어 저항(Rl) 양단에 증폭된 신호로 나타나고 영상 증폭회로(1')에서 재차 증폭된 후 처리되어 화상을 재생하게 되는바 이때 본 발명에서는 수평 편향 출력에 의한 제3도(b)로 도시된 바와같은 수평 편향 브랭킹 신호가 저항(R2),(R3)으로 된 DC 레벨 조절부(DCL)에 의하여 적절히 감쇄된 후 트랜지스터(Ql)의 베이스에 인가되어 턴온 됨으로써 트랜지스터(Q2)의 베이스 전위가 낮아져 턴오프 되는 것이다.According to the present invention, the waveform as shown in FIG. 3 (a) is input from the image amplifying circuit 1 at the time of operation of the set, and it is applied to the base of the transistor Q 2 after it has been amplified. l ) Amplified signal at both ends and amplified again in the image amplification circuit (1 ') and then processed to reproduce the image. In the present invention, the horizontal as shown in Figure 3 (b) by the horizontal deflection output base potential of being deflected probe ranking signal is the resistance (R 2), (R 3 ) to the DC level adjustment part (DCL) a suitably attenuated and then is applied to the base of the transistor (Q l) turned on by a transistor (Q 2) Is lowered and turned off.

그러므로 트랜지스터(Q2)는 수평 편향 브랭킹신호의 시간마다 주기적으로 턴오프 되어 이러한 수평 편향브랭킹신흐는 그 지속시간이 하이-비젼 방식 수평 동기신호의 지속시간 보다 매우 길게 되어 동기신호중양부분이 완전 차단되면서 영상 증폭회로(1')의 입력(In)인 저항(Rl) 일단의 전압은 제3도(c)로 보인 전압 파형을 갖게되는 것이다.Therefore, the transistor Q 2 is periodically turned off every time of the horizontal deflection blanking signal, and the horizontal deflection blanking signal has a duration longer than that of the high-vision type horizontal synchronization signal. a resistor (R l), the input (in) once the voltage of the video amplifier circuit (1 ') as full block will have to be the voltage waveform shown in FIG. 3 (c).

따라서 영상 증폭회로(1')로 출력되는 파형은 순수 영상신호와 동기신호가 완전분리된 상태가 되어 화면재생시 노이즈로 표출되는 일이 없게되어 화질을 향상시킬 수 있게되는 것이다.Accordingly, the waveform output to the image amplifying circuit 1 'is completely separated from the pure video signal and the synchronization signal, so that the image is not displayed as noise during screen reproduction, thereby improving image quality.

이와같이 하여 본 발명은 하이-비젼의 화면중 혼입되는 독특한 동기신호에 의한 화면 노이즈를 완전히 제거할 수 있게되는 것이어서, 화질을 향상시켜 품질을 개선할 수 있게 되는 유용한 발명이다.In this way, the present invention is to be able to completely remove the screen noise due to the unique synchronization signal mixed in the high-vision screen, it is a useful invention that can improve the quality by improving the image quality.

Claims (1)

영상 증폭회로(1),(1') 및 트랜지스터(Q2) 등으로 된 공지의 것에 있어서, 수평 편향 브랭킹신호가 인가되는 저항(R2),(R3)으로 DC 레벨 조절부(DCL)를 구성하고 이에 트랜지스터(Ql)의 베이스를 접속하며 그 콜렉터를 상기 트랜지스터(Q2)의 베이스와 연결되도록 함을 특징으로 하는 하이-비젼(Hi-Vision)용 영상신호 출력회로.In the well-known ones of the image amplifying circuits 1, 1 ', transistor Q 2 , etc., the DC level adjusting unit DCL is provided by resistors R 2 and R 3 to which a horizontal deflection blanking signal is applied. ) And to connect the base of the transistor (Q 1 ) and the collector to the base of the transistor (Q 2 ).
KR1019910020046A 1991-11-12 1991-11-12 Image signal output circuit of hi-vision KR940008039B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910020046A KR940008039B1 (en) 1991-11-12 1991-11-12 Image signal output circuit of hi-vision

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910020046A KR940008039B1 (en) 1991-11-12 1991-11-12 Image signal output circuit of hi-vision

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KR930011645A KR930011645A (en) 1993-06-24
KR940008039B1 true KR940008039B1 (en) 1994-09-01

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