KR960007676B1 - Atm physical layer parallel auto-synchronizing descrambler based on synchronous digital hierarchy - Google Patents

Atm physical layer parallel auto-synchronizing descrambler based on synchronous digital hierarchy Download PDF

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KR960007676B1
KR960007676B1 KR1019930004205A KR930004205A KR960007676B1 KR 960007676 B1 KR960007676 B1 KR 960007676B1 KR 1019930004205 A KR1019930004205 A KR 1019930004205A KR 930004205 A KR930004205 A KR 930004205A KR 960007676 B1 KR960007676 B1 KR 960007676B1
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atm
parallel
input
signal
physical layer
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KR1019930004205A
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KR940023094A (en
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김영섭
윤빈영
최송인
박홍식
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조백제
한국전기통신공사
양승택
재단법인 한국전자통신연구소
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

an AND operating means 24 for performing an AND operation with a data transition demixible signal and a clock; parallel input line means A0-A7 for parallelly transferring the ATM cell information of the 1-octet; a memory means 21 for inputting a clear signal to set all intial values to "0", inputting the output signal from the AND operating means 24 to a clock port and inputting an input signal from the parallel input lines A0-A7; a control means 21 for inputting the output of the memory means 22 and the data transition demixible signal(DSCENA); and an operating means 22 for inputting the control signal from the controlling means 21 and the output of the parallel input line means A0-A7, and outputting mixed signals B7-B0.

Description

동기디지탈계위(SDH) 기반 병렬 비동기 전달모드(ATM) 물리계층 병렬 자기동기 역혼화회로Synchronous Digital Threshold (SDH) -based Parallel Asynchronous Transfer Mode (ATM) Physical Layer Parallel Self-Sync Demixing Circuit

제1도는 본 발명이 적용되는 SDH 기반 ATM 물리계층 수신부 블럭구성도.1 is a block diagram of a SDH based ATM physical layer receiver according to the present invention.

제2도는 본 발명에 따른 병렬 자기동기 역혼화회로도.2 is a parallel self-synchronizing demixing circuit diagram according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 선로 정합부 12 : 프레임 처리부11: line matching unit 12: frame processing unit

11 : 헤더 에러 처리부 14 : 역혼화부11: header error processor 14: demixer

15 : ATM 계층 정합 21 : 데이터 저장부15: ATM layer matching 21: data storage

21-1 내지 21-6 : 8비트 레지스터 22 : 제어부21-1 to 21-6: 8-bit register 22: control unit

22-1 내지 22-8,24 : 앤드게이트 23 : 연산부22-1 to 22-8, 24: AND gate 23: calculation unit

23-1 내지 23-8 : 배타적 OR 게이트23-1 to 23-8: exclusive OR gate

본 발명은 CCITT 1.432에 규정된 SDH 기반 ATM 물리계층을 위한 병렬 자기동기 역혼화회로에 관한 것이다.The present invention relates to a parallel self-synchronous demixing circuit for the SDH-based ATM physical layer specified in CCITT 1.432.

일반적으로 송신단에서는 연속적인 '1'이나 '0'인 신호의 발생을 방지함으로써 수신단에서의 클럭 추출을 용이하게 하고, 전송신호를 불규칙화하여 부호간 간섭을 줄이기 위하여 전송데이타를 혼화한다. 그리고 수신단에서는 원래의 정보를 복구하여 사용자에게 전달하기 위하여 혼화된 데이타를 역혼화하여야 하므로, 1.432에 규정된 SDH 기반 ATM 물리계층의 혼화기는 특성 다항식 x43+1로 하는 자기동기 혼화회로 ATM 셀 53옥텟에 대해 헤더에 해당하는 앞의 5옥텟은 혼화를 수행하지 않고 정보부분에 해당하는 48옥텟에 대해 혼화와 동일한 특성 다항식을 갖는 자기동기 역혼화기를 통해 역혼화를 수행한다. 그런데 종래의 직렬 역혼화기를 사용하면 ATM 물리계층의 전송 속도인 155.520Mbps 혹은 622.080Mbps보다 더 빠른 동작속도를 갖는 반도체 소자로 구현하여야만 한다. 그러나 155MHz 이상으로 동작하는 반도체 소자는 고가이며 동작속도가 높아짐에 따라 회로구성이 어려워지는 문제점이 있다.In general, the transmitting end facilitates clock extraction at the receiving end by preventing the occurrence of continuous '1' or '0' signals, and mixes transmission data to reduce inter-code interference by irregularizing the transmission signal. In order for the receiving end to recover the original information and transmit it back to the user, the mixed data of the SDH-based ATM physical layer specified in 1.432 has to have a characteristic polynomial x 43 +1. The first five octets corresponding to the header for the octets are not mixed, but the back-mixing is performed through the self-synchronizing demixer having the same characteristic polynomial as the mixing for the 48 octets corresponding to the information part. However, if a conventional serial demixer is used, it must be implemented as a semiconductor device having an operation speed higher than that of the transmission speed of the ATM physical layer, which is 155.520 Mbps or 622.080 Mbps. However, there is a problem that the semiconductor device operating at 155MHz or more is expensive and the circuit configuration becomes difficult as the operating speed increases.

상기 문제점을 해결하기 위하여 안출된 본 발명은, 일반적인 반도체 소자를 이용하여 전송데이타를 8비트 병렬로 처리하므으로써 회로의 동작속도를 155.520Mbps의 전송 속도인 경우 19.44Mbps로 처리할 수 있도록 한 ATM 물리계층을 위한 병렬 자기동기 역혼화회로를 제공하는데 그 목적이 있다.In order to solve the above problems, the present invention, by processing the transmission data in 8-bit parallel using a general semiconductor device, the operation speed of the circuit can be processed to 19.44Mbps when the transmission speed of 155.520Mbps Its purpose is to provide a parallel self-synchronizing demixing circuit for the layer.

상기 목적을 달성하기 위하여 본 발명인 SDH 기반 ATM 물리계층을 위한 병렬 자기동기 역혼화회로는, 전송매체로부터 데이타를 수신하는 선로 정합부와, 상기 선로 정합부에서 수신된 데이타로부터 ATM 셀을 추출하기 위한 프레임 처리부와, 상기 프레임 처리부에 연결되어 ATM 셀 헤더의 에러를 검출하고 교정하는 헤더 에러 처리부와, 상기 프레임 처리부에 연결되고 혼화되어 있는 셀의 사용자 정보를 역혼화하기 위한 역혼화부와, 상기 헤더 에러 처리부를 통해 수신된 ATM 셀을 ATM 계층으로 전달하기 위한 ATM 계층 정합부로 구성된 SDH 기반 ATM 물리계층 수신수단에 적용되는 역혼화부에 있어서 ; 클럭을 일입력으로 하고 데이타 천이 역혼화 가능신호(DSCENA)를 타입력으로 하여 논리곱 연산하는 앤드수단. ATM 셀인 1옥텟의 정보를 병렬로 전송하기 위한 병렬 입력라인수단(A7~A0), 초기치를 모두 '0'으로 하기 위한 클리어신호를 클리어단자로 입력받고, 상기 앤드수단으로부터의 출력신호를 클럭단자로 입력받으며, 전송데이타의 상기 병렬 입력라인수단(A0~A7)으로부터 ATM 셀인 입력신호를 입력단자(D7~D0)로 입력받는 데이타 저장수단, 상기 데이타 저장수단의 출력을 일입력으로받고 상기 DSCENA 신호를 타입력으로 하는 제어수단, 상기 제어수단으로부터의출력을 일입력으로 하고 상기 병렬 입력라인수단(A7~A0)을 타입력으로 하여 1옥텟의 최종 출력신호(B7~B0)를 내는 연산수단을 구비하고 있는 것을 특징으로 한다.In order to achieve the above object, a parallel self-synchronizing demiscible circuit for the SDH-based ATM physical layer of the present invention includes a line matching unit for receiving data from a transmission medium and an ATM cell from the data received at the line matching unit. A frame error processing unit, a header error processing unit connected to the frame processing unit to detect and correct an error of an ATM cell header, a demixing unit for demixing user information of a cell connected and mixed with the frame processing unit, and the header error A demixing unit applied to an SDH-based ATM physical layer receiving unit comprising an ATM layer matching unit for delivering an ATM cell received through a processing unit to the ATM layer; End means for performing a logical AND operation using a clock as one input and a data transition demixable signal (DSCENA) as a type force. Parallel input line means A7 to A0 for parallel transmission of one octet of information, which is an ATM cell, and a clear signal for setting all initial values to '0' as a clear terminal, and an output signal from the end means as a clock terminal. A data storage means for receiving an input signal, which is an ATM cell, from the parallel input line means A0 to A7 of transmission data to an input terminal D7 to D0, and receiving the output of the data storage means as one input; Control means for making a signal a type force, an arithmetic means for producing one octet of final output signals B7 to B0 with the output from the control means as one input and the parallel input line means A7 to A0 as a type force. It is characterized by having a.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제1도는 본 발명이 적용되는 SDH 기반 ATM 물리계층 수신부 블럭 구성도로서, 도면에서 11은 선로 정합부, 12는 프레임 처리부, 11은 헤더 에러 처리부, 14는 역혼화부, 15는 ATM 계층 정합부를 각각 나타낸다.FIG. 1 is a block diagram of an SDH-based ATM physical layer receiver according to the present invention, in which 11 is a line matching unit, 12 is a frame processing unit, 11 is a header error processing unit, 14 is a demixing unit, and 15 is an ATM layer matching unit. Indicates.

도면에 도시한 바와 같이 SDH 기반 ATM 물리계층 수신부는, 전송매체로부터 데이타를 수신하는 선로 정합부(11)와, 상기 선로 정합부(11)에서, 수신된 데이타로부터 ATM 셀을 추출하기 위한 프레임 처리부(12)와, 상기 프레임 처리부(12)에 연결되어 ATM 셀 헤더의 에러를 검출하고 교정하는 헤더 에러 처리부(13)와, 상기프레임 처리부(12)에 연결되고 혼화되어 있는 셀의사용자 정보를 역혼화하기 위한 역환화부(14)와, 상기 역혼화부(14)와 상기 헤더 에러 처리부(13)를 통해 수신된 ATM 셀을 ATM 계층으로 전달하기 위한 ATM 계층 정합부(15)로 구성된다.As shown in the figure, the SDH-based ATM physical layer receiver includes a line matching unit 11 for receiving data from a transmission medium, and a frame processing unit for extracting an ATM cell from the received data in the line matching unit 11. (12), a header error processor (13) connected to the frame processor (12) for detecting and correcting errors in an ATM cell header, and user information of a cell connected to and mixed with the frame processor (12). It consists of an inverse summation section 14 for mixing, and an ATM layer matching section 15 for delivering ATM cells received through the inverse mixing section 14 and the header error processing section 13 to an ATM layer.

제2도는 SDH 기반 ATM 물리계층의 역혼화를 위한 병렬 자기동기 역혼화부(제1도의 14)의 회로도로서, 도면에서 21은 데이타 저장부, 21-1 내지 21-6은 8비트 레지스터, 22는 제어부, 22-1 내지 22-8,24는 앤드게이트, 23은 연산부, 23-1 내지 23-8은 배타적 OR 게이트를 각각 나타낸다.2 is a circuit diagram of a parallel self-synchronizing demixing unit (14 in FIG. 1) for demixing an SDH-based ATM physical layer, in which 21 is a data storage unit, 21-1 to 21-6 are 8-bit registers, and 22 is The controllers 22-1 to 22-8 and 24 denote AND gates, 23 denotes arithmetic units, and 23-1 to 23-8 denote exclusive OR gates, respectively.

도면에 도시한 바와 같이, 병렬 자기동기 역혼화기는, 19.44Mbps의 클럭을 일입력으로 하고 데이타 천이 역혼화 가능신호(DSCENA)를 타입력으로 하는 앤드게이트(24)로부터의 출력신호를 클럭단자로 입력받으며, 전송데이타의 병렬 입력단자(A0~A7)로부터 추출된 ATM 셀을 입력단자(D7~D0)로 입력받는 데이타 저장부(21), 상기 데이타 저장부(21)의 출력을 일입력으로 받고 상기 DSCENA 신호를 타입력으로 하는 제어부(22), 상기 제어부(22)로부터의 출력을 일입력으로 하고 상기 입력신호인 ATM 셀(A7~A0)을 타입력으로 하여 배타적 논리합 처리한 후 최종 출력신호(B7~B0)를 내는 연산부(23)로 구성된다.As shown in the figure, the parallel self-synchronizing demultiplexer uses the clock of 19.44 Mbps as one input and the output signal from the AND gate 24 having the data transition demixing possible signal DSCENA as the type force as the clock terminal. The data storage unit 21 receives the ATM cell extracted from the parallel input terminals A0 to A7 of the transmission data through the input terminals D7 to D0, and outputs the data storage unit 21 as one input. The control unit 22 having the DSCENA signal as the type force and the output from the control unit 22 as one input, and processing the exclusive OR using the ATM cells A7 to A0 as the input signal as the type force and then outputting the final output. It consists of the calculating part 23 which outputs signals B7-B0.

상기 구성에 대한 동작을 살펴보면, 출력신호(B7~B0)는 상기 DSCENA가 '로우'인 동안에는 제어부(22)의 출력신호 '0'이므로 연산부(23)는 입력데이타인 ATM 셀을 그대로 출력하고 상기 DSCENA가 '하이'인 동안에는 역혼화된 데이타를 출력한다. 즉, 초기화시에 클리어신호를 이용하여 데이타 저장부(21)를 모두 '0'으로 만든다. 그리고, 헤더가 시작되는 시점에서 5옥텟의 데이타가 입력되기까지 DSCENA 신호는 '로우' 상태가 되어 입력되는 데이타가 그대로 출력되고 나머지 48옥텟의 데이타가 입력되는 동안 DSCENA 신호를 '하이' 상태로 만들면 입력되는 데이타와 데이타 저장부(21)를 토래 지연된 데이타와 연산부(23)에서 가산을 수행하여 혼화된 데이타로부터 원래의 정보를 추출하여 출력하고 데이타 저장부(21)의 데이타는 8비트씩 다음 레지스터로 천이된다.Referring to the operation of the configuration, the output signal (B7 ~ B0) is the output signal '0' of the control unit 22 while the DSCENA is 'low', so the operation unit 23 outputs the ATM cell as the input data as it is and While DSCENA is 'high', the demixed data is output. That is, the data storage unit 21 is set to '0' by using the clear signal at the time of initialization. Then, when the header starts, the DSCENA signal becomes 'low' until 5 octets of data are input, and the input data is output as it is, and the DSCENA signal is 'high' while the remaining 48 octets of data are input. The input data and the data storage unit 21 are added by the delayed data and the calculation unit 23 to extract and output the original information from the mixed data, and the data of the data storage unit 21 is the next register by 8 bits. As it transitions.

따라서, 상기와 같은 본 발명에 의하여 자기동기 역혼화기를 병렬로 구현할 경우 고가의 고속 반도체 소자를 사용하지 않고도 회로를 구현할 수 있으며 높은 주파수에 따라 발생하는 제반 문제점을 해결할 수 있게 됨으로써 SDH 기반 ATM 물리계층의 역혼화 생성기에 적용하면 데이타 전송 속도에 구애받지 않고 회로를 설계할 수 있는 효과가 있다.Accordingly, when the self-synchronizing demixer is implemented in parallel according to the present invention, a circuit can be implemented without using an expensive high-speed semiconductor device and the various problems caused by the high frequency can be solved. When applied to the demixing generator of, it is possible to design the circuit regardless of the data transfer rate.

Claims (4)

전송매체로부터 데이타를 수신하는 선로 정합부(11)와, 상기 선로 정합부(11)에서 수신된 데이타로부터 ATM 셀을 추출하기 위한 프레임 처리부(12)와, 상기 프레임 처리부(12)에 연결되어 ATM 셀 헤더의 에러를 검출하고 교정하는 헤더 에러 처리부(13)와, 상기 프레임 처리부(12)에 연결되고 혼화되어 있는 셀의 사용자 정보를 역혼화하기 위한 역혼화부(14)와, 상기 역혼화부(14)와, 상기 헤더 에러 처리부(13)를 통해 수신된 ATM 셀을 ATM 계층으로 전달하기 위한 ATM 계층 정합부(15)로 구성된 SDH 기반 ATM 물리계층 수신수단에 적용되는 역혼화부(14)에 있어서, 클럭을 일입력으로 하고 데이타 천이 역혼화 가능신호(DSCENA)를 타입력으로 하여 논리곱 연산하는 앤드수단(24) ; ATM 셀인 1옥텟의 정보를 병렬로 전송하기 위한 병렬 입력라인수단(A7~A0) ; 초기치를 모두 '0'으로 하기 위한 클리어신호를 클리어단자로 입력받고, 상기 앤드수단(24)으로부터의 출력신호를 클럭단자로 입력받으며, 전송데이타의 상기 병렬 입력라인수단(A0~A7)으로부터 ATM 셀인 입력신호를 입력단자(D7~D0)로 입력받는 저장수단(21) ; 상기 저장수단(21)의 출력을 일입력으로 받고 상기 DSCENA 신호를 타입력으로 하는 제어수단(22) ; 상기 제어수단(22)으로부터의 출력을 일입력으로 하고 상기 병렬 입력라인수단(A7~A0)을 타입력으로 하여 1옥텟의 최종 출력신호(B7~B0)를 내는 연산수단(23)을 구비하는 것을 특징으로 하는 SDH 기반 ATM 물리계층을 위한 병렬 자기동기 역혼화회로.A line matching section 11 for receiving data from a transmission medium, a frame processing section 12 for extracting an ATM cell from the data received at the line matching section 11, and an ATM connected to the frame processing section 12 A header error processor 13 for detecting and correcting an error of a cell header, a demixer 14 for demixing user information of a cell connected and mixed with the frame processor 12, and the demixer 14 In the demixing unit 14 applied to the SDH-based ATM physical layer receiving means composed of the ATM layer matching unit 15 for transferring the ATM cell received through the header error processing unit 13 to the ATM layer, End means 24 for performing a logical AND operation using the clock as one input and the data transition demixable signal DSCENA as a type force; Parallel input line means (A7 to A0) for transmitting one octet of information, which is an ATM cell, in parallel; A clear signal for setting all of the initial values to '0' is inputted to a clear terminal, an output signal from the end means 24 is input to a clock terminal, and ATM is transmitted from the parallel input line means A0 to A7 of transmission data. Storage means (21) for receiving a cell input signal through input terminals (D7 to D0); Control means (22) for receiving the output of the storage means (21) as one input and for making the DSCENA signal a type force; And an arithmetic means 23 for outputting the output from the control means 22 as one input and outputting one final octet of the final output signals B7 to B0 using the parallel input line means A7 to A0 as a type force. Parallel self-synchronizing inverse circuit for the SDH-based ATM physical layer, characterized in that. 제1항에 있어서, 상기 저장수단(22)은 ; 8비트 레지스터로 구성된 것을 특징으로 하는 SDH 기반 병렬 비동기 전달모드(ATM) 물리계층을 위한 병렬 자기동기 역혼화회로.The method according to claim 1, wherein the storage means (22); Parallel self-synchronizing demixing circuit for SDH-based parallel asynchronous transfer mode (ATM) physical layer, characterized by an 8-bit register. 제1항에 있어서, 상기 연산수단(23)은 ; 다수의 배타적 논리합수단으로 구성된 것을 특징으로 하는 SDH 기반 병렬 비동기 전달모드(ATM) 물리계층을 위한 병렬 자기동기 역혼화회로.The method according to claim 1, wherein said calculating means (23) comprises; Parallel self-synchronizing demixing circuit for SDH-based parallel asynchronous transfer mode (ATM) physical layer, characterized in that it comprises a plurality of exclusive logical sum means. 제1항에 있어서, 상기 제어수단(22)은 ; 8개의 앤드게이트를 구비하고 있는 것을 특징으로 하는 SDH 기반 병렬 비동기 전달모드(ATM) 물리계층을 위한 병렬 자기동기 역혼화회로.2. The apparatus according to claim 1, wherein said control means (22) comprises; Parallel self-synchronizing demixing circuit for SDH-based parallel asynchronous transfer mode (ATM) physical layer, characterized by having eight end gates.
KR1019930004205A 1993-03-18 1993-03-18 Atm physical layer parallel auto-synchronizing descrambler based on synchronous digital hierarchy KR960007676B1 (en)

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