KR960006500A - Timing Integrated Circuits (ICs) - Google Patents

Timing Integrated Circuits (ICs) Download PDF

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Publication number
KR960006500A
KR960006500A KR1019940018274A KR19940018274A KR960006500A KR 960006500 A KR960006500 A KR 960006500A KR 1019940018274 A KR1019940018274 A KR 1019940018274A KR 19940018274 A KR19940018274 A KR 19940018274A KR 960006500 A KR960006500 A KR 960006500A
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KR
South Korea
Prior art keywords
horizontal
counting
vertical
predetermined
signal
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Application number
KR1019940018274A
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Korean (ko)
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KR100243363B1 (en
Inventor
임경석
Original Assignee
이대원
삼성항공산업 주식회사
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Priority to KR1019940018274A priority Critical patent/KR100243363B1/en
Publication of KR960006500A publication Critical patent/KR960006500A/en
Application granted granted Critical
Publication of KR100243363B1 publication Critical patent/KR100243363B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

본 발명은 CCD 카메라에 관한 것으로, 상세하게는 CCD 카메라에 사용되는 타이밍 IC에 관한 것이다.The present invention relates to a CCD camera, and more particularly, to a timing IC used in a CCD camera.

상세하게는, 본 발명에 따른 타이밍 IC는 2개의 카운터와 2개의 조합/순차 회로부와 1개의 게이트부로써, 간단하게 2의 승수배가 아닌 분주 신호를 생성할 수 있으므로, 구성 게이트와 레지스터의 수가 적고, 구동 소비 전력 또한 줄어들어 경제적이며, 회로 자체가 간단한 장점이 있다.Specifically, the timing IC according to the present invention has two counters, two combination / sequential circuit sections, and one gate section, and can generate a divided signal rather than a multiplier of two, so that the number of configuration gates and registers is small. In addition, the driving power consumption is also reduced and economical, and the circuit itself has a simple advantage.

Description

타이밍 직접 회로(IC)Timing Integrated Circuits (ICs)

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 종래의 타이밍 IC의 내부 블럭도.1 is an internal block diagram of a conventional timing IC.

제2도는 본 발명에 따른 타이밍 IC에 추가되는 회로의 블럭도.2 is a block diagram of a circuit added to a timing IC according to the present invention.

〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

1 : 수평 카운터부 2 : 수직 카운터부1: horizontal counter 2: vertical counter

3 : 수평 조합/순차 회로부 4 : 수직 조합/순차 회로부3: Horizontal combination / sequential circuit part 4: Vertical combination / sequential circuit part

5 : 게이트부5: gate part

Claims (4)

촬상 소자의 수평 화소의 수를 카운트해 주는 수평 카운트 수단과, 상기 촬상 소자의 수직 화소의 수를 카운트해 주는 수직 카운트 수단과, 상기 수평 카운트 수단에서 일정한 수만큼 카운트하고, 다시 처음부터 그 일정수 까지 카우트하는 반복 작업을 할 수 있도록 일정수 만큼 카운트되었을 때, 다시 초기 상태로 돌아갈 수 있도록 초기화시켜 주는 신호를 만들어 주는 리세트 수단과, 셔터 속도를 제어할 수 있도록 하는 신호를 만들어 주는 셔터 제어 수단과, 상기 수평 카운트 수단으로 부터 카운트된 소정의 개수의 수평 화소 신호를 조합하거나 순차적으로 내보내어 소정의 제1중간 신호를 만들어 주는 수평 조합/순차 수단과, 상기 수직 카운트 수단으로 부터 카운트된 소정의 개수의 수직 화소 신호를 조합하거나 순차적으로 내보내어 소정의 제2중간 신호를 만들어 주는 수직 조합/순차 수단과, 상기 수평 조합/순차 수단 및 상기 수직 조합/순차 수단으로 부터 출력된 제1중간 신호 및 제2중간 신호를 인가받아 이를 논리적으로 조합하여 소망하는 신호를 만들어 주는 게이트 논리 수단을 구비하는 것을 특징으로 하는 타이밍 집적 회로.Horizontal counting means for counting the number of horizontal pixels of the image pickup device, vertical counting means for counting the number of vertical pixels of the image pickup device, and a predetermined number of counts in the horizontal counting means, and the number of the predetermined number from the beginning again. Reset means for generating a signal to reset to the initial state when a certain number is counted to repeat the operation to count, and shutter control to create a signal to control the shutter speed Means, horizontal combining / sequential means for combining or sequentially outputting a predetermined number of horizontal pixel signals counted from said horizontal counting means to form a predetermined first intermediate signal, and predetermined counting from said vertical counting means Combines a plurality of vertical pixel signals or sequentially exports a predetermined second of Vertical combinations / sequence means for making the inter-signal, and first and second intermediate signals outputted from the horizontal combinations / sequence means and the vertical combinations / sequence means are received and logically combined to obtain desired signals. And a gate logic means for making the timing integrated circuit. 제1항에 있어서, 수평 카운트 수단은 수평 주사를 위한 1820개의 클럭을 카운트하는 점에 특징이 있는 타이밍 집적 회로.2. The timing integrated circuit according to claim 1, wherein the horizontal counting means counts 1820 clocks for horizontal scanning. 제1항에 있어서, 수직 카운트 수단은 홀수 필드와 짝수 필드로 이루어진 전체 주사수 525의 절반딘 262.5에서 시작하는 짝수 필드 신호를 만들기 위하여 525 주사수의 2배인 1050개의 클럭을 카운트하는 점에 특징이 있는 타이밍 집적 회로.2. The method of claim 1, wherein the vertical counting means is characterized by counting 1050 clocks, twice the number of 525 scans, to produce an even field signal starting at 262.5 of the total number of scans 525 consisting of odd and even fields. Timing integrated circuit. 제1항에 있어서, 수평 및 수직 조합/순차 수단은 프로그래머블 로직 어레이로 형성된 점에 특징이 있는 타이밍 집적 회로.2. The timing integrated circuit according to claim 1, wherein the horizontal and vertical combination / sequential means are formed in a programmable logic array. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940018274A 1994-07-27 1994-07-27 Timing ic KR100243363B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940018274A KR100243363B1 (en) 1994-07-27 1994-07-27 Timing ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940018274A KR100243363B1 (en) 1994-07-27 1994-07-27 Timing ic

Publications (2)

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KR960006500A true KR960006500A (en) 1996-02-23
KR100243363B1 KR100243363B1 (en) 2000-02-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030037011A (en) * 2001-11-01 2003-05-12 주식회사 미토스엠텍 Amplifier Circuit for Enable to Transform Output Voltage

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030037011A (en) * 2001-11-01 2003-05-12 주식회사 미토스엠텍 Amplifier Circuit for Enable to Transform Output Voltage

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KR100243363B1 (en) 2000-02-01

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