KR960005238Y1 - Pll with a constant loop gain - Google Patents

Abstract

None.

Description

Phase Locked Loop (PLL) with Constant Loop Gain

1 is a schematic circuit diagram of a conventional phase locked loop.

2 is a schematic circuit diagram of a phase locked loop according to the present invention.

* Explanation of symbols for main parts of the drawings

1, 10: multiplier 2, 20: first amplifier

3, 30: voltage controlled oscillator (VCO) 4, 50: second amplifier

50: comparator

The present invention relates to a phase locked loop that can obtain a constant loop gain regardless of the magnitude of an input signal.

In the conventional phase locked loop, an automatic gain control circuit (AGC) or a bandpass limiter (BPL) has been used to obtain a constant loop gain. However, when using an AGC circuit, an envelope detector and a voltage control are used. There is a disadvantage in that the structure is complicated by using an amplifier, and in the case of using a band pass limiter, there is a problem in that the output signal size varies with the input signal frequency.

Referring to FIG. 1 to describe this in more detail, in the drawing, 1 denotes a multiplier, 2 denotes an amplifier, and 3 denotes a voltage controlled oscillator (VCO).

Here, when the magnitude of the input signal is S ₁ , the magnitude of the output signal of the voltage controlled oscillator 3 is Sv, the gain of the amplifier 2 is k ₁ , and the sensitivity of the VCO 3 is kv. The loop gain K ₂ of the phase locked loop of FIG. 1 is obtained by the following equation.

K _L = S ₁ SvK ₁ Kv / 2... … … … … (One)

In Equation (1), since Sv, K ₁ , and Kv are constants, but S ₁ is a variable, it can be seen that the loop gain K _L varies according to the magnitude of the input signal S ₁ .

In order to prevent the loop gain from changing according to the input signal and to always obtain a constant loop gain, the phase locked loop according to the present invention includes a multiplier to which an input signal is applied, a resistor and a capacitor. A first low pass filter connected to a multiplier for passing only low frequency components, a first amplifier for amplifying an output signal from the first low pass filter, and between the first amplifier and the multiplier, the output of which is A phase locked loop comprising a voltage controlled oscillator configured to be fed back to a multiplier, comprising: a second amplifier connected to the multiplier, a second low pass filter connected to the second amplifier, and one connected to the second low pass filter. It has an input and another input connected to the input signal, and an output terminal is connected to the first low pass filter. It characterized in that it comprises a comparator.

The phase locked loop according to the present invention is described in detail with reference to FIG. 2 as follows.

As can be seen from FIG. 2, in the phase locked loop according to the present invention, the conventional phase locked loop includes a second amplifier 40 for amplifying the output signal from the multiplier 10, and the second amplifier. The low pass filter (R3, C2) for blocking the high frequency components and outputting only the low frequency components in the output signal of the comparator and the comparator 50 for comparing the input signal with the output signal from the low pass filter was configured.

In such a configuration, the input signal X ₁ and the output signal X ₄ of the VOC 30 are as follows.

X ₁ = S ₁ .Sin {2πft + δ (t)}. … … … (2)

X ₄ = Sv.Cos {2πft + ψ (t)}... … … … (3)

Where S ₁ is the magnitude of the input signal.

Sv is the magnitude of the output signal of the VCO.

Next, the input signal X ₁ and the output signal X ₄ of the VCO 3 are multiplied by the multiplier 10, and then only low frequency components are passed through the low pass filter to be applied to the comparator 50.

Therefore, the input signal X ₂ of one input of the comparator 50 is obtained as follows.

_{X 2 = (S 1 SvK 2} /2) Sinφ (t) ... … … … (4)

Where φ (t) = (δ) (t) −ψ (t), and K ₂ is the gain of the second amplifier.

In addition, the low frequency component X3 of the comparator 50 output is as follows. In other words,

The loop gain K _L of the phase locked loop according to the present invention is obtained from Equation (5) as follows.

K _L = (2 / [pi]) EK ₁ Kv... … … … … … … (6)

Therefore, as can be seen from Equation (6), since the loop gain K _L of the phase locked loop according to the present invention does not include the variable size of the input signal S ₁ , the loop gain is constant regardless of the magnitude of the input signal. It can be seen that this is obtained.

Therefore, according to the present invention, it is possible to obtain a phase locked loop which always has a constant loop gain.

Claims (1)

A multiplier to which an input signal is applied, a resistor and a capacitor, a first low pass filter connected to the multiplier for passing only low frequency components, and a first low pass filter for amplifying an output signal from the first low pass filter. A phase locked loop comprising an amplifier and a voltage controlled oscillator coupled between the first amplifier and the multiplier, the output of which is fed back to a multiplier, comprising: a second amplifier coupled to the output of the multiplier for amplifying the output signal And a second low pass filter connected to an output of the second amplifier to block high frequency components of the output signal and to pass only low frequency components, and one input connected to an output of the second low pass filter and another connected to an input signal. And a comparator having an input and an output coupled to said first low pass filter. A phase lock loop having a constant loop gain.