JPH06169254A - Pll circuit - Google Patents
Pll circuitInfo
- Publication number
- JPH06169254A JPH06169254A JP43A JP34331992A JPH06169254A JP H06169254 A JPH06169254 A JP H06169254A JP 43 A JP43 A JP 43A JP 34331992 A JP34331992 A JP 34331992A JP H06169254 A JPH06169254 A JP H06169254A
- Authority
- JP
- Japan
- Prior art keywords
- output
- input
- circuit
- operational amplifier
- amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】この発明はPLL回路についての
ものであり、特に電圧制御発振器の入力に混入する外来
雑音によるスペクトル劣化を抑制するPLL回路につい
てのものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit, and more particularly to a PLL circuit which suppresses spectrum deterioration due to external noise mixed in the input of a voltage controlled oscillator.
【0002】[0002]
【従来の技術】従来技術によるPLL回路の構成を図2
に示す。図2の1は位相比較器、3は電圧制御発振器、
4は分周器、5はループフィルタである。図2で、ルー
プフィルタ5は、入力回路5A、演算増幅器5E、帰還
回路5Bからなり、低域通過フィルタを構成している。
図2で、電圧制御発振器3の出力は2分配され、一方は
分周器4の入力に接続される。位相比較器1は外部から
基準信号入力端子1Aに入力される信号と、比較信号入
力端子1Bに入力される分周器4の出力信号の位相差を
検出し、位相差に応じた電圧を出力する。この位相検出
器1の出力はループフィルタ5の入力に接続される。ル
ープフィルタ5は、PLL回路のループ特性を決定づけ
るとともに、位相比較器1の出力信号に含まれる高い周
波数成分を除去し、電圧制御発振器3にしゅつりょくす
る。2. Description of the Related Art The configuration of a PLL circuit according to the prior art is shown in FIG.
Shown in. 2, 1 is a phase comparator, 3 is a voltage controlled oscillator,
Reference numeral 4 is a frequency divider, and 5 is a loop filter. In FIG. 2, the loop filter 5 comprises an input circuit 5A, an operational amplifier 5E, and a feedback circuit 5B, and constitutes a low pass filter.
In FIG. 2, the output of the voltage controlled oscillator 3 is divided into two, one of which is connected to the input of the frequency divider 4. The phase comparator 1 detects a phase difference between a signal externally input to the reference signal input terminal 1A and an output signal of the frequency divider 4 input to the comparison signal input terminal 1B, and outputs a voltage according to the phase difference. To do. The output of this phase detector 1 is connected to the input of the loop filter 5. The loop filter 5 determines the loop characteristic of the PLL circuit, removes a high frequency component contained in the output signal of the phase comparator 1, and causes the voltage controlled oscillator 3 to switch.
【0003】[0003]
【発明が解決しようとする課題】図2に示すループフィ
ルタ5を用いたPLL回路では、ループの帯域を広げる
場合、ループフィルタを構成する演算増幅器には、利得
帯域幅積の大きなものを用いる必要があった。しかし、
利得帯域幅積の大きな演算増幅器は、一般に直流利得が
低いため、電圧制御発振器3の入力に混入する外来雑音
を充分抑圧できないという問題がある。この発明は、電
圧制御発振器3の入力に混入する外来雑音を抑圧し、ス
ペクトル純度の高いPLL回路を実現することを目的と
する。In the PLL circuit using the loop filter 5 shown in FIG. 2, when the band of the loop is widened, it is necessary to use a large gain bandwidth product as the operational amplifier forming the loop filter. was there. But,
Since an operational amplifier having a large gain bandwidth product generally has a low DC gain, there is a problem that external noise mixed in the input of the voltage controlled oscillator 3 cannot be suppressed sufficiently. An object of the present invention is to suppress the external noise mixed in the input of the voltage controlled oscillator 3 and realize a PLL circuit with high spectral purity.
【0004】[0004]
【課題を解決するための手段】この目的を達成するた
め、この発明では、基準信号入力端子1Aに入力する信
号と比較信号入力端子1Bに入力する信号の位相差を検
出し、位相差に応じた電圧を出力する位相比較器1と、
位相比較器1からの出力信号を入力するループフィルタ
2と、ループフィルタ2からの出力電圧に応じた周波数
を持つ信号を出力する電圧制御発振器3と、電圧制御発
振器3からの出力信号を分周し、分周後の信号を位相比
較器1の比較信号入力端子に出力する分周器4とを有す
るPLL回路において、ループフィルタ2は、位相比較
器1の出力を入力とする入力回路2Aと、入力回路2A
の出力を反転入力端子に入力する演算増幅器2Cと、算
増幅器2Cの出力を入力とする減衰器2Dと、入力回路
2Aの出力を反転入力端子の入力とし、減衰器2Dの出
力を非反転入力端子の入力とする演算増幅器2Eと、演
算増幅器2Eの出力と入力とし、入力回路2Aの出力と
接続する帰還回路2Bとを備える。In order to achieve this object, the present invention detects a phase difference between a signal input to a reference signal input terminal 1A and a signal input to a comparison signal input terminal 1B, and detects the phase difference according to the phase difference. And a phase comparator 1 that outputs a voltage,
The loop filter 2 that inputs the output signal from the phase comparator 1, the voltage-controlled oscillator 3 that outputs a signal having a frequency corresponding to the output voltage from the loop filter 2, and the output signal from the voltage-controlled oscillator 3 are frequency-divided. Then, in the PLL circuit having the frequency divider 4 which outputs the frequency-divided signal to the comparison signal input terminal of the phase comparator 1, the loop filter 2 has an input circuit 2A whose input is the output of the phase comparator 1. , Input circuit 2A
Operational amplifier 2C for inputting the output of the input to the inverting input terminal, attenuator 2D for inputting the output of the operational amplifier 2C, and output of the input circuit 2A for inputting the inverting input terminal, and output for the attenuator 2D is non-inverting It includes an operational amplifier 2E which is an input of the terminal, and a feedback circuit 2B which is an input to the output of the operational amplifier 2E and is connected to the output of the input circuit 2A.
【0005】[0005]
【作用】次に、この発明によるPLL回路の構成を図1
に示す。図1の2はループフィルタであり、他は図2と
同じである。ループフィルタ2は、入力回路2Aと、入
力回路2Aの出力を反転入力端子に入力する演算増幅器
2Cと、演算増幅器2Cの出力を入力とする減衰器2D
と、減衰器2Dの出力を非反転入力端子の入力とし、入
力回路2Aの出力を反転入力端子の入力とする演算増幅
器2Eと、演算増幅器の出力を入力回路2Aの出力に帰
還する帰還回路2Bとを備える。Next, the configuration of the PLL circuit according to the present invention is shown in FIG.
Shown in. Reference numeral 2 in FIG. 1 is a loop filter, and the others are the same as those in FIG. The loop filter 2 includes an input circuit 2A, an operational amplifier 2C for inputting the output of the input circuit 2A to an inverting input terminal, and an attenuator 2D for inputting the output of the operational amplifier 2C.
And an operational amplifier 2E having the output of the attenuator 2D as the input of the non-inverting input terminal and the output of the input circuit 2A as the input of the inverting input terminal, and a feedback circuit 2B for feeding back the output of the operational amplifier to the output of the input circuit 2A. With.
【0006】ループフィルタ2で、入力回路2Aと演算
増幅器2Eと帰還回路2Bは、図2のループフィルタ5
の入力回路5Aと演算増幅器5Eと帰還回路5Bと同じ
である。この発明では、図2に示す回路における演算増
幅器5Eに代わり、演算増幅器2Cと、減衰器2Dと、
演算増幅器2Eとを組み合わせたものを用い、PLL回
路を構成している。In the loop filter 2, the input circuit 2A, the operational amplifier 2E and the feedback circuit 2B are the loop filter 5 of FIG.
The input circuit 5A, operational amplifier 5E, and feedback circuit 5B are the same. In the present invention, instead of the operational amplifier 5E in the circuit shown in FIG. 2, an operational amplifier 2C, an attenuator 2D, and
A PLL circuit is configured using a combination with the operational amplifier 2E.
【0007】演算増幅器2Cと演算増幅器2Eとを組み
合わせることにより、利得帯域幅積が大きく、同時に直
流利得の大きな増幅器の特性を得て、電圧制御発振器3
の入力に混入する外来雑音を大きく抑圧する。By combining the operational amplifier 2C and the operational amplifier 2E, the characteristics of the amplifier having a large gain bandwidth product and a large direct current gain can be obtained, and the voltage controlled oscillator 3 can be obtained.
It greatly suppresses the external noise mixed in the input of.
【0008】[0008]
【実施例】次に、この発明による場合と従来技術による
場合における、電圧制御発振器の入力に外来雑音が混入
した時のPLL回路の出力位相の変動量の比較結果を図
3に示す。ここで、PLLのループ帯域を 400kHzと
し、入力回路2Aは 150Ωの抵抗器を使用する。帰還回
路2Bは 1.1kΩの抵抗器と1000pFのコンデンサを直
列接続し、演算増幅器2Cの開ループ時の直流利得は 1
20dB、演算増幅器2Cの利得帯域幅積は7MHz、演
算増幅器2Eの開ループ時の直流利得は75dB、演算増
幅器2Eの利得帯域幅積は50MHzとする。FIG. 3 shows the comparison result of the fluctuation amount of the output phase of the PLL circuit when the external noise is mixed in the input of the voltage controlled oscillator in the case of the present invention and the case of the conventional technique. Here, the loop band of the PLL is 400 kHz, and the input circuit 2A uses a resistor of 150Ω. The feedback circuit 2B has a 1.1kΩ resistor and a 1000pF capacitor connected in series, and the DC gain when the operational amplifier 2C is open loop is 1
The gain bandwidth product of the operational amplifier 2C is 20 dB, the direct current gain of the operational amplifier 2E is 75 dB, and the gain bandwidth product of the operational amplifier 2E is 50 MHz.
【0009】また、演算増幅器5Eの開ループ時の直流
利得は75dB、演算増幅器5Eの利得帯域幅積は50MH
z、減衰器2Dの減衰量は60dB、分周器4の分周比は
1/64という回路定数を用いている。図3において、aは
この発明による場合の結果、bは従来技術による場合の
結果を示しており、この発明によれば、従来より最大で
60dB改善されている。The open-loop DC gain of the operational amplifier 5E is 75 dB, and the gain bandwidth product of the operational amplifier 5E is 50 MH.
z, the attenuation amount of the attenuator 2D is 60 dB, and the frequency division ratio of the frequency divider 4 is
The circuit constant of 1/64 is used. In FIG. 3, a shows the result in the case of the present invention and b shows the result in the case of the conventional technique.
It is improved by 60 dB.
【0010】[0010]
【発明の効果】この発明によれば、2つの演算増幅器と
減衰器を組み合わせたものをループフィルタに用いるこ
とにより、電圧制御発振器の入力に混入する外来雑音を
抑圧し、スペクトル純度の高いPLL回路を実現するこ
とができる。According to the present invention, by using a combination of two operational amplifiers and an attenuator for the loop filter, the external noise mixed in the input of the voltage controlled oscillator is suppressed, and the PLL circuit having high spectral purity. Can be realized.
【図1】この発明によるPLL回路の実施例の構成図で
ある。FIG. 1 is a configuration diagram of an embodiment of a PLL circuit according to the present invention.
【図2】従来技術によるPLL回路の構成図である。FIG. 2 is a configuration diagram of a PLL circuit according to a conventional technique.
【図3】この発明による場合と従来技術による場合にお
ける、電圧制御発振器の入力に外来雑音が混入した時の
PLL回路の出力位相の変動量の比較結果である。FIG. 3 is a comparison result of the fluctuation amount of the output phase of the PLL circuit when the external noise is mixed in the input of the voltage controlled oscillator in the case of the present invention and the case of the conventional technique.
1 位相比較器 2 ループフィルタ 3 電圧制御発振器 4 分周器 5 ループフィルタ 2A 入力回路 2B 帰還回路 2C 演算増幅器 2D 減衰器 2E 演算増幅器 1 phase comparator 2 loop filter 3 voltage controlled oscillator 4 frequency divider 5 loop filter 2A input circuit 2B feedback circuit 2C operational amplifier 2D attenuator 2E operational amplifier
Claims (1)
比較信号入力端子(1B)に入力する信号の位相差を検出
し、位相差を電圧量に変換する位相比較器(1) と、位相
比較器(1) の出力信号を入力するループフィルタ(2)
と、ループフィルタ(2) の出力電圧に応じた周波数を持
つ信号を出力する電圧制御発振器(3) と、電圧制御発振
器(3) の出力信号を分周し、分周後の信号を位相比較器
(1) の比較信号入力端子に出力する分周器(4) とを備え
るPLL回路において、 ループフィルタ(2) は、位相比較器(1) の出力を入力と
する入力回路(2A)と、 入力回路(2A)の出力を反転入力端子に入力する第1の演
算増幅器(2C)と、 第1の演算増幅器(2C)の出力を入力とする減衰器(2D)
と、 入力回路(2A)の出力を反転入力端子の入力とし、減衰器
(2D)の出力を非反転入力端子の入力とする第2の演算増
幅器(2E)と、 第2の演算増幅器(2E)の出力と入力とし、入力回路(2A)
の出力と接続する帰還回路(2B)とを備えることを特徴と
するPLL回路。1. A phase comparator (1) for detecting a phase difference between a signal input to a reference signal input terminal (1A) and a signal input to a comparison signal input terminal (1B) and converting the phase difference into a voltage amount. , Loop filter (2) that inputs the output signal of the phase comparator (1)
And the voltage control oscillator (3) that outputs a signal with a frequency according to the output voltage of the loop filter (2) and the output signal of the voltage control oscillator (3) are frequency-divided, and the signals after frequency division are compared in phase. vessel
In the PLL circuit including the frequency divider (4) that outputs to the comparison signal input terminal of (1), the loop filter (2) has an input circuit (2A) that receives the output of the phase comparator (1), A first operational amplifier (2C) that inputs the output of the input circuit (2A) to the inverting input terminal, and an attenuator (2D) that inputs the output of the first operational amplifier (2C)
And the output of the input circuit (2A) as the input of the inverting input terminal.
The second operational amplifier (2E), which uses the output of (2D) as the input of the non-inverting input terminal, and the output and input of the second operational amplifier (2E), and the input circuit (2A)
And a feedback circuit (2B) connected to the output of the PLL circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP43A JPH06169254A (en) | 1992-11-30 | 1992-11-30 | Pll circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP43A JPH06169254A (en) | 1992-11-30 | 1992-11-30 | Pll circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH06169254A true JPH06169254A (en) | 1994-06-14 |
Family
ID=18360605
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP43A Pending JPH06169254A (en) | 1992-11-30 | 1992-11-30 | Pll circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06169254A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009016996A (en) * | 2007-07-02 | 2009-01-22 | Kawasaki Microelectronics Kk | Phase-locked loop circuit |
JP2015070314A (en) * | 2013-09-26 | 2015-04-13 | 日本電波工業株式会社 | Pll circuit |
-
1992
- 1992-11-30 JP JP43A patent/JPH06169254A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009016996A (en) * | 2007-07-02 | 2009-01-22 | Kawasaki Microelectronics Kk | Phase-locked loop circuit |
JP2015070314A (en) * | 2013-09-26 | 2015-04-13 | 日本電波工業株式会社 | Pll circuit |
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