KR960001891Y1 - Smps delay circuit - Google Patents
Smps delay circuit Download PDFInfo
- Publication number
- KR960001891Y1 KR960001891Y1 KR2019910005379U KR910005379U KR960001891Y1 KR 960001891 Y1 KR960001891 Y1 KR 960001891Y1 KR 2019910005379 U KR2019910005379 U KR 2019910005379U KR 910005379 U KR910005379 U KR 910005379U KR 960001891 Y1 KR960001891 Y1 KR 960001891Y1
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- South Korea
- Prior art keywords
- transistor
- delay circuit
- capacitor
- circuit
- smps
- Prior art date
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/338—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in a self-oscillating arrangement
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
- Electronic Switches (AREA)
Abstract
내용 없음.No content.
Description
제1도는 본 고안을 해결하기 위한 회로도1 is a circuit diagram for solving the present invention
제2도의 (a)도는 지연회로가 없는 스위칭 트랜지스터 "온" 시 손실 파형도이고.FIG. 2 (a) is a loss waveform diagram of the switching transistor “on” without a delay circuit.
(b)도는 지연회로가 있는 스위칭 트랜지스터 "온" 시 손실 파형도이다.(b) is a loss waveform diagram of " on " a switching transistor with a delay circuit.
제3도의 (a)도는 링깅 쵸크 콘버터 회로의 VoE 및 IC 파형도Fig. 3 (a) is a VoE and IC waveform diagram of a ringing choke converter circuit.
(b)도는 콜렉터 및 에미터의 용량에 의한 트랜지스터 "오프"시 손실파형도(b) is a loss waveform diagram when transistor "off" due to the capacity of the collector and emitter
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 앰프 2 : 트랜스1: amplifier 2: transformer
3 : 지연회로 4 : 스피드업(Speed up)회로3: delay circuit 4: speed up circuit
TR1, TR2 : 트랜지스터 D1∼D4 : 다이오드TR1, TR2: transistors D1 to D4: diode
R1∼R5 : 저항 C1∼C4 : 콘덴서R1 to R5: resistors C1 to C4: capacitors
본 고안은 링깅 쵸크 컨버터(Ringing Choke Converter : RCC)방식을 사용한 스위칭 모드 파우어 서플라이(Switching Mode Power Supply : 이하SMPS라함) 지연회로에 관한 것으로, 특히 스위칭 트랜지스터 "온"시에 발생하는 손실(Loss)을 줄여 SMPS의 효율을 향상시키기 위한 스위칭 모드 파우어 서플라이 지연회로에 관한 것이다.The present invention relates to a switching mode power supply (SMPS) delay circuit using a ringing choke converter (RCC) method, in particular, a loss occurring when the switching transistor is turned on. The present invention relates to a switching mode power supply delay circuit for reducing the efficiency of SMPS.
종래의 SMPS회로는 별도의 지연회로가 없어 스위칭 트랜지스터 "온"시에 발생하는 손실로 인해 스위칭 트랜지스터에서 과다한 열이나므로써 출력 효율이 불안정하여 트랜지스터의 출력효을을 향상시키기 위한 수단으로 규모가 큰 방열판을 사용해야 되는 문제점이 발생하였던 것이다.Conventional SMPS circuits do not have a separate delay circuit, and due to the loss generated at the time of switching transistor "on" due to excessive heat in the switching transistor, the output efficiency is unstable, and a large heat sink is used as a means for improving the output efficiency of the transistor. There was a problem that must be used.
본 고안에서는 상기한 제반 결점을 해소하기 위한 것으로, 그 목적으로는 일정시간 지연시키는 지연회로를 SMPS회로에 부가하여 스위칭 트랜지스터 "온"시에 발생하는 손실을 최대한 줄여 SMPS회로의 출력효율을 향상시킬 수 있도록 함에 있다.The present invention is to solve the above-mentioned shortcomings, and for this purpose, a delay circuit for delaying a predetermined time is added to the SMPS circuit to reduce the loss occurring at the time of switching ON, thereby improving the output efficiency of the SMPS circuit. It is in making it possible.
본 고안의 다른 목적은 지연회로를 SMPS회로에 부가하여 스의칭 트랜지스터 "온"시에 발생하는 손실을 최대한 줄여 SMPS회로의 방열판을 적게하여 신뢰성을 향상시킴에 있다.Another object of the present invention is to add a delay circuit to the SMPS circuit to minimize the loss occurring at the time of the switching transistor "on" to reduce the heat sink of the SMPS circuit to improve the reliability.
본 고안은 트랜스(2) 드라이브권선(D)의 "오프"전압을 충전하는 콘덴서(C1)와 상기 콘덴서(C1)방전시 트랜지스터(TR1)에 정전압을 공급하는 다이오드(D2)(D4)와 저항(R3)으로 된 지연회로(3)를 구비한 것이 주지적인 특징이다.The present invention provides a capacitor (C1) for charging the "off" voltage of the transformer (2) drive winding (D) and a diode (D2) (D4) and a resistor for supplying a constant voltage to the transistor (TR1) during discharge of the capacitor (C1). It is a well-known feature to have a delay circuit 3 of R3.
이를 첨부 도면에 의해 설명한다.This will be described with reference to the accompanying drawings.
저항(R4)을 통해 입력되는 전원(Vin)을 스위칭용 트랜지스터(TR2) Q베이스와 트랜지스터(TR1) 콜렉터 및 스피드업회로(4) 일측단에 인가하고 트랜스(2) 1차측권선(P)을 트랜지스터(TR2) 콜렉터에 접속하되, 상기 트랜지스터(TR2) 콜렉터와 에미터 사이에는 "오프"시 손실을 감소하는 콘덴서(C3)를 연결하고, 트랜스(2)드라이브권선(D)이 스피드업회로(4) 타측단과 앰프(1)에 접속된 SMPS회로에 있어서,A power supply Vin input through the resistor R4 is applied to one end of the switching transistor TR2, the Q base, the transistor TR1, and the speed up circuit 4, and the transformer 2 primary winding P is applied. A transistor C3 is connected between the transistor TR2 collector and the transistor < RTI ID = 0.0 > TR2 < / RTI > 4) In the SMPS circuit connected to the other end and the amplifier 1,
상기 트랜스(2) 드라이브권선(D)의 "오프"전압을 충전하는 콘덴서(C1)와 상기 콘덴서(C1)방전시 트랜지스터(TR1)에 정전압을 공급하는 다이오드(D2)(D4)와 저항(R3)으로 된 지연회로(3)를 구비한다.A capacitor C1 that charges the " off " voltage of the drive winding D of the transformer 2, and a diode D2, D4, and a resistor R3 that supply a constant voltage to the transistor TR1 when the capacitor C1 discharges. A delay circuit (3) is provided.
이하 첨부된 도면에 의해 본 고안에 따른 작용 및 효과를 설명하면 다음과 같다.Referring to the operation and effects according to the present invention by the accompanying drawings as follows.
제1도는 본 고안을 해결하기 위한 회로도이다.1 is a circuit diagram for solving the present invention.
입력되는 전원(Vin)이 저항(R4)을 경유하여 트랜지스터(TR2) 베이스에 인가됨과 아울러 트랜스(2)1차측권선(P)을 통해 트랜지스터(TR2) 콜렉터에 인가된다The input power supply Vin is applied to the transistor TR2 base via the resistor R4 and is applied to the transistor TR2 collector through the transformer 2 primary side winding P.
상기 트랜지스러(TR2)에 전원(Vin)이 인가되므로써, 상기 트랜지스터(TR2)가 "온"된다.The power supply Vin is applied to the transistor TR2, so that the transistor TR2 is "on".
상기 트랜지스터(TR2)가 "온"이 되므로 인하여 이의 콜렉터와 에미터에 접속된 콘덴서(C3)의 방전전류가앰프(1)에 가해져서 제2도의 (a)도에 도시한 파형도와 같이 트랜지스터(TR2)의 전류가 급격히 증대하게 된다.Since the transistor TR2 is turned "on", the discharge current of the capacitor C3 connected to the collector and the emitter thereof is applied to the amplifier 1, so that the transistor (as shown in the waveform of FIG. The current of TR2) increases rapidly.
한편 전원(Vin)이 차단되어 스위칭 작용을 하는 트랜지스터(TR2)가 "오프"시에는 이의 콜렉터와 에미터에 접속딘 콘덴서(C3)의 충전전압에 의해 손실이 감소된다.On the other hand, when the transistor TR2, which switches off and switches the power supply Vin "off", the loss is reduced by the charging voltage of the capacitor C3 connected to the collector and the emitter thereof.
따라서 트랜지스터(TR2)의 "온"시에 전류의 증대에 관한 손실의 증가를 콘덴서(C1)와 다이오드(D2)(D3)와 저항(R3)으로된 지연회로(3)에 의해 트랜지스터(TR2)의 손실을 절감시킬 수 있다.Therefore, the increase of the loss related to the increase of the current when the transistor TR2 is turned on is caused by the delay circuit 3 composed of the capacitor C1, the diode D2, the D3, and the resistor R3. Can reduce the loss.
즉, 트랜스(2) 드라이브권선(D)의 "오프"전압을 이용해서 지연회로(3)의 다이오드(D2)와 저항(R3)을 통해 콘덴서(C1)에 충전한다.That is, the capacitor C1 is charged through the diode D2 and the resistor R3 of the delay circuit 3 using the " off " voltage of the transformer 2 drive winding D.
상기 콘덴서(C1)에 충전이 완료된 상태에서 트랜지스터(TR2)가 "온"시에 콘덴서(C1)에 충전된 전류를 방전한다.The transistor TR2 discharges the current charged in the capacitor C1 when the transistor TR2 is " on " while the capacitor C1 is completely charged.
상기 지연회로(3)의 콘덴서(C1)에서 방전되는 전류는 트랜지스러(TR1) 베이스에 인가되어 상기 트랜지스터(TR1)를 "온"시켜 트랜스(2) 드라이브권선(D)에 전류가 있는 시간 동안만 유기시킨다.The current discharged from the capacitor C1 of the delay circuit 3 is applied to the base of the transistor TR1 to turn on the transistor TR1 so that the current in the transformer 2 drive winding D is present. Organic only.
상기 트랜스(2) 드라이브권선(D)에 전류가 있는 시간 동안만 유기되어 콘덴서(C1)의 방전이 끝날 때까지 트랜지스터(TR2)는 "온"상태를 유지하여 정상 응답이 정지되는 데드타임(Dead Time)을 생성한다.Dead time in which the transistor TR2 remains in the "on" state until the discharge of the capacitor C1 is completed until the discharge of the capacitor C1 is terminated only during the time when the current in the drive winding D of the transformer 2 is dead. Create a Time).
그결과 트랜지스터(TR2)의 콜렉터와 에미터간의 전압이 낮은 단자에 트랜지스터(TR2)의 "온"시에 전류가 흘러 제2도의 (b)도에 도시한 파형도와 같이 트랜지스터(TR2)의 손실을 절감한다.As a result, a current flows in the terminal of the transistor TR2 having a low voltage between the collector and the emitter at " on " of the transistor TR2, thereby reducing the loss of the transistor TR2 as shown in the waveform diagram of FIG. Save.
상술한바와 같이 본 고안은 일정시간 지연시키는 지연회로를 SMPS회로에 부가하여 스위칭 트랜지스터 "온"시에 발생하는 손실을 최대한 줄여 SMPS회로의 출력 효율을 향상시킴과 아울러 방열판을 적게하여 SMPS회로의 신뢰성을 향상시킬 수 있는 것이다.As described above, the present invention adds a delay circuit for a certain time delay to the SMPS circuit, thereby minimizing the loss occurring at the time of switching on, thereby improving the output efficiency of the SMPS circuit, and reducing the heat sink to reduce the reliability of the SMPS circuit. To improve.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019910005379U KR960001891Y1 (en) | 1991-04-18 | 1991-04-18 | Smps delay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019910005379U KR960001891Y1 (en) | 1991-04-18 | 1991-04-18 | Smps delay circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920020361U KR920020361U (en) | 1992-11-17 |
| KR960001891Y1 true KR960001891Y1 (en) | 1996-02-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019910005379U KR960001891Y1 (en) | 1991-04-18 | 1991-04-18 | Smps delay circuit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR960001891Y1 (en) |
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1991
- 1991-04-18 KR KR2019910005379U patent/KR960001891Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR920020361U (en) | 1992-11-17 |
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