KR960001471B1 - Vitervi decoder - Google Patents

Abstract

a plurality of memory elements having a selector and a delay element, the memory element being connected between an adding comparator and a checking part; and a path memory part for using an living path information transmitted from the adding comparator as a switch signal of the selector, and transferring data selected by the living path to the next terminal by adjusting it with a reception data clock.

Description

Viterbi Decoder

1 is a block diagram of a conventional Viterbi decoder.

FIG. 2 is a detailed configuration diagram of the path tracking logic unit and the path memory unit employed in the first-to-be bibiter decoding ratio.

3 is a lattice diagram in the case of decoding a signal encoded by a convolutional code having a code ratio R = 1/2 and a constraint length K = 3.

4 is a configuration diagram of a Viterbi decoder according to the present invention.

FIG. 5 is an exemplary view of a path memory device employed in the Viterbi decoder shown in FIG.

* Explanation of symbols for main parts of the drawings

10: Jiro evaluation amount calculation part 20: Addition comparison selection part

30: state evaluation amount storage unit 40, 40 ': path storage unit

50: maximum likelihood determining unit 60: path tracking logic unit

1A to 12A: Delay elements 1B to 8B: 2 x 1 selector

1C: 4 × 1 selector

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi decoder for correcting errors occurring on a transmission path in a digital transmission system. More particularly, the present invention relates to a path memory element, that is, a Viterbi decoder that reduces the complexity of a circuit and increases processing speed by reconfiguring a path memory. .

In general, the Viterbi decoder uses the Maximum Likelihood Decoding Method to search for the largest log-likelihood function among several paths on the Trellis Diagram, and thus the series of paths It is a device that decodes the data encoded by Convolutional Code by adopting Albitorithm which estimates the transmitted code sequence. In addition, since the bit-to-bit decoder has a very good decoding gain among the decoders decoded by the convolutional code, it is used when the quality of the transmission path is bad or the signal strength is limited.

As shown in FIG. 1, a typical bitter ratio decoder includes a branch metric quantity calculation unit 40, a maximum likelihood determination unit 50, and a path tracking logic unit 60.

Referring to the operation according to the configuration of FIG. 1, first, the evaluation amount calculation unit 10 calculates an approximation based on the order of the data received from the receiver (not shown here) and the code data that can be output from the encoder. .

The addition comparison selecting unit 20 adds the state evaluation amount of the previous state stored in the evaluation amount state evaluation amount storage unit 30 calculated by the branch evaluation amount calculation unit 10, compares and closest to the code order of the transmitted data. Survival maps of each state are selected, and the state evaluation amount of the selected road is stored in the state evaluation amount storage unit 30, and the road information is stored in the path storage unit 40, respectively.

At this time, the maximum likelihood determination unit 50 finds the state with the largest likelihood function and inputs it to the path tracking logic unit 60, and the path tracking logic unit 60 tracks the information as stored in the path storage unit 40. Decoded data is output by finding the path closest to the path of the data sent from the transmitter.

As described above, the detailed configuration diagram of the path storage section 40 and the path tracking logic section 60 is shown in FIG.

Referring to the operation according to the configuration of FIG. 2, the RAM 40A of the path storage section 40 receives and stores the information (b) of the survival road in the giro joining the respective states from the addition comparison selecting section 20. The shift register 60A of the path tracking logic section 60 uses the address b of the state where the logwood function transmitted from the maximum likelihood determining section 50 is the maximum to use the RAM 40A of the path storage section 40. Read the information as it is stored in. At this time, the shift register 60A of the path tracking logic unit 60 generates the row address of the front end and transmits it to the RAM 40A, which causes the RAM 40A to be 4 to 5 times the constraint length. After the information is traced back to the past, the decoded data is output. In order to explain the above operation, FIG. 3 shows a part of a trellis diagram when decoding a signal encoded by a convolutional code having a code ratio R = 1/2 and a constraint length K = 3.

Returning to FIG. 2 again, the addition comparison selecting unit 20 selects a path having a large state evaluation amount among the two girders joining each state, and transmits the information to the RAM 40A of the path storage unit 40 to the survival place of each state. Save it. In this case, since there are four states, there are four branches of PS0, PS1, PS2, and PS3. Since two branches of each branch join each state, PSi (i = 0, 1, 2, 3) is represented by 1 bit. Can be broken. In addition, each branch joining each state can be used as an indicator for the address of the previous state, so PSi is displayed as 0 when the upper branch is selected and 1 when the lower branch is selected. At the time t, while the branch information of each state is stored in the RAM 40A of the path memory 40, the address generated by the column address generator 40B is changed from 0 to 3. On the other hand, the shift register 60A of the path tracking logic section 60 receives the address of the state having the maximum state evaluation amount from the maximum likelihood determining section 50, and is 4 to 5 times the constraint length K (in this case, 12 to 15). Tracking), where the address of the address generator 40B is decremented one by one, and the address of the shift register 60A received from the rightmost discrimination unit 50 is continuously changed by the information read from the RAM 40A. It generates a row address corresponding to a survival path. When all of the reverse tracking is completed, the RAM 40A outputs the most significant bit (MSB) of the row address remaining in the shift register 60A as decoded data. The above operation is repeated every time.

Usually, the processing speed of the decoder depends on the processing speed of the addition comparison selecting unit 20 and the time required for path tracking. The addition comparison selecting unit 20 can be connected in parallel to increase the calculation speed, but the RAM ( The path storage unit 40 using 40A) has no choice but to write and read one data at a time, so that the main clock needs as many as the number of states to write information. There was a problem that it is necessary to limit the processing speed.

In a circuit using a memory element such as the RAM 40A, since a logic circuit for memory addressing of read and write operations must be specified in a complicated order as in the above example, a large delay time is generated. Since the access time to write and read data is considerable, the conventional Viterbi decoder having the path storage unit 60 is limited in processing speed by the time required for path tracking, even when using a fast memory element. There is another problem that cannot be used in the decoding process.

Accordingly, an object of the present invention is to provide a Viterbi decoder capable of processing data faster than the conventional technology by providing a path storage unit that does not require path tracking.

Another object of the present invention is to provide a new memory device that minimizes the access time that is a problem when using an existing memory device, thereby providing a high-speed data processing.

It is still another object of the present invention to provide a path memory that does not require a memory address generator when using a conventional memory device, thereby reducing the complexity of the circuit and providing a reliable bitter ratio decoder.

In order to achieve the above object, the present invention is a bitter ratio decoder including a branch evaluation calculation unit, an addition comparison selection unit, a state evaluation amount storage unit and a maximum likelihood determination unit, connected between the addition comparison selection unit and the maximum likelihood determination unit. And a plurality of memory elements including a delay element, using information as a surviving destination transmitted from the addition comparison selector, as a switching signal of the selector, and sending the surviving destination to the surviving data of the input data stored in the delay element. And a path storage unit for moving the data selected by the information to the next stage simultaneously with the received data clock.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

4 is a configuration diagram of a Viterbi decoder according to the present invention, which has a feature that does not have a path tracking logic unit in comparison with the conventional Viterbi decoder shown in FIG. 1, except for the path storage unit 40 '. The structure and function are the same as the conventional Viterbi decoder.

FIG. 5 is a diagram showing an example of the path storage unit 40 'employed in the biter ratio decoder shown in FIG. 4 and configured as an example in the case of code ratio R- = 1/2 and restriction length K = 3. If the K value is changed, the number of delay elements and the 2x1 selector changes regularly so that description thereof is omitted.

5 is a look at the operation according to the configuration.

Each of the delay elements 1A to 12A constituted by the D flip flop is used as a storage element for storing data and simultaneously performs write-in and read-out operations. Also, the 2x1 selectors 1B-4B located at the front end of the delay elements 5A-8A are shown in FIG. 3 according to the survival route information PSi from the addition comparison selecting section 20 shown in FIG. It is configured to select the data of the previous state corresponding to the trellis diagram. At this time, the surviving route information PSi does not change during one receive data clock, and the data of each delay element 1A to 4A is moved to the next delay elements 5A to 6A selected by PSi in accordance with the receive data clock. On the other hand, no separate 2x1 selector is connected to the first delay elements 1A to 4A, and the input data of the delay elements 1A to 2A is always "0" and the other half of the delay elements 3A and 4A. The input data of is always "1". The operation of the path storage section having such a configuration is repeated for each received data clock.

As can be seen from the lattice diagram in the case of decoding a coded signal of convolutional code having the code ratio R = 1/2 and the constraint length K = 3 shown in FIG. 3, all the branches joining the states S0 and S1 at the time point t It can be seen that the transition to the input data " 0 " of the transmitting encoder is a transition to the input data " 1 " of the transmitting encoder. Using this transition principle, the corresponding input data is stored in each delay element 1A to 4A as a living place instead of the information PSi, and the stored data is stored in the grid as shown in FIG. Passing along the same path to the next step makes path tracking unnecessary. That is, as shown in FIG. 5, the input data of the delay elements 1A and 2A corresponding to the states S0 and S1 are always "0" for each time point, and the delay elements 3A and 4A corresponding to S2 and S3 are shown. The input data is always "1".

On the other hand, the information PSi on the survival road output from the addition comparison selection unit 20 uses the information as a switching means of the lattice diagram and uses the information of the delay elements 1A to 4A input at the time t at the time t + 1. The delay paths 5A to 8A are passed along the survival path. If the point of time reaches t + 1 (4 to 5 times the binding length) during this operation, the input data at the point in time reaches the delay elements 9A to 12A along the survival path. The contents of the delay elements 9A to 12A corresponding to the address received from (50) are output as decoded data through the 4x1 selector (4x1 MUX) 1C.

As described above, according to the present invention, in order to eliminate the time required for path tracking, the path tracking is performed by configuring memory elements (RAM and RAM) of the path storage unit using the characteristics of the lattice diagram with a plurality of selectors and delay elements having a fast data transition time. Decoding is performed at every data reception time, thereby eliminating the need for a circuit for addressing memory addresses (RAM and RAM) of the main clock generator and the path memory section, which is much faster than the path tracer and the received data clock. A simple circuit has the advantage of enabling faster data processing.

Claims (1)

A bitter ratio decoder comprising a branch evaluation evaluation unit, an addition comparison selection unit, a state evaluation amount storage unit and a maximum likelihood discrimination unit, comprising: a plurality of memory elements connected between the addition comparison selection unit and the maximum likelihood discrimination unit and including a selector and a delay element; And using the surviving destination information transmitted from the addition comparison selecting unit as a switching signal of the selector, and converting the data selected by the surviving destination information among the input data of the transmitting encoder stored in the delay element to the reception data clock. Viterbi decoder characterized in that it comprises a path memory for moving to the next stage at the same time.