KR950035175A - Clock failure detection device - Google Patents

Clock failure detection device Download PDF

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Publication number
KR950035175A
KR950035175A KR1019940010341A KR19940010341A KR950035175A KR 950035175 A KR950035175 A KR 950035175A KR 1019940010341 A KR1019940010341 A KR 1019940010341A KR 19940010341 A KR19940010341 A KR 19940010341A KR 950035175 A KR950035175 A KR 950035175A
Authority
KR
South Korea
Prior art keywords
signal
clock
failure
communication device
clock failure
Prior art date
Application number
KR1019940010341A
Other languages
Korean (ko)
Other versions
KR970002944B1 (en
Inventor
윤용석
Original Assignee
박성규
대우통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 박성규, 대우통신 주식회사 filed Critical 박성규
Priority to KR1019940010341A priority Critical patent/KR970002944B1/en
Publication of KR950035175A publication Critical patent/KR950035175A/en
Application granted granted Critical
Publication of KR970002944B1 publication Critical patent/KR970002944B1/en

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766Error or fault reporting or storing
    • G06F11/0772Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers

Abstract

본 발명은 통신 장치에서 사용되는 클록의 장애를 검출하기에 적합한 클록 장애 검출 장치에 관한 것으로, 종래에는 클록에 장애가 발생하면 통신 장치의 기능이 마비되는 등 통신 장치의 대부분의 기능에 심각한 장애가 초래되었으나, 본 발병에서는 디지탈 회로를 사용하는 통신 장치 등에서 사용하는 클록에 장애가 발생할 경우 이를 검출하여 프로세서 등의 해당 제어부측에 알려주어 적합한 조치가 이루어지도록 함으로써 상기 결점을 개선시킬 수 있는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock failure detection device suitable for detecting a failure of a clock used in a communication device. In the related art, when a failure occurs in a clock, a serious failure occurs in most functions of the communication device, such as paralyzing the function of the communication device. In this case, the fault can be improved by detecting a failure in a clock used in a communication device using a digital circuit, and informing a corresponding control unit such as a processor so that appropriate measures can be taken.

Description

클록 장애 검출 장치Clock failure detection device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

도면은 본 발명에 따른 클록 장애 검출 장치의 일 실시예를 나타낸 블럭도.Figure is a block diagram showing an embodiment of a clock failure detection apparatus according to the present invention.

Claims (2)

클록과 감시용 신호를 비교하는 비교부(1)와; 상기 비교부(1)의 신호를 클리어 신호로 인가 받아 클록을 카운트하고 카운터(2)와; 상기 카운터(2)의 신호를 인가 받아 인에이블 신호에 따라 클록 장애시 인터럽트 신호를 출력하는 인터럽트 발생부(4)와; 상기 카운트(2)의 신호와 감시용 신호를 인가받아 클록 장애시 클록 장애 상태를 저장하며 장애된 클록의 종류를 디스플레이 하는 상태 표시부(3)와; 상기 인터럽트 발생부(3)의 신호를 인가 받아 인에이블 신호에 따라 클록 장애시 인터럽트 신호를 해당 제어부측에 인가하기 위한 논리합회로(5)를 포함하여 이루어지는 클록 장애 검출 장치.A comparator 1 for comparing a clock and a monitoring signal; A counter (2) is counted by receiving the signal of the comparator (1) as a clear signal; An interrupt generator (4) which receives the signal of the counter (2) and outputs an interrupt signal when a clock fails in accordance with an enable signal; A status display unit (3) for receiving the signal of the count (2) and the monitoring signal to store a clock failure state in case of a clock failure and to display the type of the failed clock; And a logic sum circuit (5) for receiving a signal from the interrupt generator (3) and applying an interrupt signal to a corresponding controller in case of a clock failure in accordance with an enable signal. 제1항에 있어서, 상기 감시용 신호로 클록보다 높은 주파수를 갖는 신호를 사용함을 특징으로 하는 클록 장애 검출 장치.The apparatus of claim 1, wherein a signal having a higher frequency than a clock is used as the monitoring signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940010341A 1994-05-12 1994-05-12 Apparatus for detecting a clock abstacle KR970002944B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940010341A KR970002944B1 (en) 1994-05-12 1994-05-12 Apparatus for detecting a clock abstacle

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940010341A KR970002944B1 (en) 1994-05-12 1994-05-12 Apparatus for detecting a clock abstacle

Publications (2)

Publication Number Publication Date
KR950035175A true KR950035175A (en) 1995-12-30
KR970002944B1 KR970002944B1 (en) 1997-03-13

Family

ID=19382906

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940010341A KR970002944B1 (en) 1994-05-12 1994-05-12 Apparatus for detecting a clock abstacle

Country Status (1)

Country Link
KR (1) KR970002944B1 (en)

Also Published As

Publication number Publication date
KR970002944B1 (en) 1997-03-13

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