KR950029903A - Aimed Digital Clock Loss Detector - Google Patents

Aimed Digital Clock Loss Detector Download PDF

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Publication number
KR950029903A
KR950029903A KR1019940008480A KR19940008480A KR950029903A KR 950029903 A KR950029903 A KR 950029903A KR 1019940008480 A KR1019940008480 A KR 1019940008480A KR 19940008480 A KR19940008480 A KR 19940008480A KR 950029903 A KR950029903 A KR 950029903A
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South Korea
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clock
counter
signal
loss detector
predetermined
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KR1019940008480A
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Korean (ko)
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KR960010912B1 (en
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이상용
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박성규
대우통신 주식회사
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

본 발명은 디지탈적으로 신호를 처리하고 에이직 집적회로(Application Specific IC)를 사용한 클럭손실 검출기에 관한 것으로, 기준클럭을 카운트하여 기설정된 카운트 값에 도달하면 소정의 신호를 발생하는 카운터부(100)와, 측정클럭의 존재 유무를 판정하는 클럭을 발생하는 클럭 연산기(200)와, 기설정된 카운트 시간동안 상기 클럭 연산기(200)의 클럭 발생 여부에 따라 상기 측정클럭의 존재를 판정하는 클럭손실 판정기(300)를 포함하여 구성함으로써, 기준클럭만 입력되면 해당 클럭의 손실 유무를 판단할 수 있으며, 디지탈적으로 신호를 처리하는 에이직 회로를 사용하므로 소형화가 가능하다.내용 없음BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock loss detector that digitally processes a signal and uses an application specific IC. The counter unit 100 generates a predetermined signal when the reference clock is counted and a predetermined count value is reached. ), A clock calculator 200 for generating a clock for determining the presence of a measurement clock, and a clock loss plate for determining the presence of the measurement clock according to whether the clock calculator 200 has a clock for a predetermined count time. By including the periodic 300, if only the reference clock is input, it is possible to determine whether or not the clock is lost, it is possible to miniaturize because the digital circuit processing signal is used.

Description

에이직화한 디지탈 클럭손실 검출기Aimed Digital Clock Loss Detector

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 실시예에 따른 에이직화한 디지탈 클럭 손실 검출기의 개략적인 블럭도, 제3도는 본 발명의 실시예에 따른 에이직화한 디지탈 클럭 손실 검출기의 상세 회로도.2 is a schematic block diagram of an integrated digital clock loss detector according to an embodiment of the present invention, and FIG. 3 is a detailed circuit diagram of an integrated digital clock loss detector according to an embodiment of the present invention.

Claims (11)

클럭손실 검출기에 있어서, 기준클럭을 카운트하여 기설정된 카운트 값에 도달하면 소정의 신호를 발생하는 카운터부(100)와; 측정클럭의 존재 유무를 판정하는 클럭을 발생하는 클럭 연산기(200)와; 기설정된 카운트 시간동안 상기 클럭 연산기(200)의 클럭 발생 여부에 따라 상기 측정클럭의 존재를 판정하는 클럭손실 판정기(300)를 포함하는 에이직화한 디지탈 클럭손실 검출기.A clock loss detector, comprising: a counter unit (100) for counting a reference clock and generating a predetermined signal when a predetermined count value is reached; A clock calculator 200 for generating a clock for determining whether a measurement clock is present; An integrated digital clock loss detector including a clock loss determiner (300) for determining the presence of the measurement clock according to whether or not the clock generator (200) has a clock for a predetermined count time. 제1항에 있어서, 상기 카운터부(100)는, 상기 기준클럭을 입력받은 후, 상기 기준클럭을 2분주한 클럭을 입력 데이타로 하여 그 시간차만큼 지연되어 출력하는 분주수단(110)과, 상기 분주수단(110)으로 부터 제공된 상기 입력 데이타를 카운트하여 기설정된 카운트 값에 도달하면 소정의 신호를 발생하는 제1카운터 수단(120)과, 상기 제1카운터 수단(120)으로 부터 발생된 상기 신호를 입력받아 기설정된 카운트 값에 도달하면 소정의 신호를 발생하는 제2카운트 수단(130)을 더 포함하는 에이직화한 디지탈 클럭손실 검출기.According to claim 1, The counter unit 100, After receiving the reference clock, the frequency divider means for dividing the clock divided by two the reference clock as input data delayed by the time difference and outputs the, A first counter means 120 for generating a predetermined signal when the input data provided from the dividing means 110 is counted to reach a predetermined count value, and the signal generated from the first counter means 120; And a second count means (130) for generating a predetermined signal upon receiving a predetermined count value. 제1 또는 2항에 있어서, 상기 클럭 연산기(200)는, 상기 측정클럭을 입력받은 후, 상기 측정클럭을 2분주한 클럭을 입력 데이타로 하여 그 시간차만큼 지연되어 출력하는 분주수단(210)과, 상기 분주수단(210)으로부터 제공된 상기 입력 데이타를 카운트하여 기설정된 카운트 값에 도달하면 상기 측정클럭의 존재 유무를 판정하는 클럭신호를 발생하는 카운터 수단(220)을 더 포함하는 에이직화한 디지탈 클럭손실 검출기.3. The clock operator 200 according to claim 1 or 2, wherein the clock calculator 200 divides the clock by dividing the measurement clock into two input clocks, and outputs the delayed signal by a time difference. And a counter means 220 which counts the input data provided from the dispensing means 210 and generates a clock signal for determining the presence or absence of the measurement clock when a predetermined count value is reached. Loss detector. 제3항에 있어서, 상기 클럭손실 판정기(300)는, 상기 기설정된 카운트 시간 동안 상기 카운터 수단(220)으로 부터 클럭신호가 발생하면 로우신호를 출력하고, 상기 기설정된 카운트 시간 동안 상기 카운터 수단(220)으로부터 클럭신호가 발생되지 않으면 하이신호를 출력하는 판정수단(310)을 더 포함하는 에이직화한 디지탈 클럭손실 검출기.The counter of claim 3, wherein the clock loss determiner 300 outputs a low signal when a clock signal is generated from the counter means 220 during the preset count time, and outputs the low signal during the preset count time. And a determining means (310) for outputting a high signal if a clock signal is not generated from (220). 제4항에 있어서, 상기 카운터부(100)의 상기 분주수단(110)은 D플립플럽인 것을 특징으로 하는 에이직화한 디지탈 클럭손실 검출기.5. The digital clock loss detector of claim 4, wherein the dispensing means (110) of the counter unit (100) is a D flip flop. 제4항에 있어서, 상기 카운터부(100)의 상기 제1카운터 수단(120)은 16진 카운터인 것을 특징으로 하는 에이직화한 디지탈 클럭손실 검출기.5. The digital clock loss detector of claim 4, wherein the first counter means of the counter part (100) is a hexadecimal counter. 제4항에 있어서, 상기 카운터부(100)의 상기 제2카운터 수단(130)은 8진 카운터인 것을 특징으로 하는 에이직화한 디지탈 클럭손실 검출기.5. The digital clock loss detector of claim 4, wherein the second counter means (130) of the counter part (100) is an octal counter. 제4항에 있어서, 상기 클럭 연산기(200)의 상기 분주수단(210)은 D플립플럽인 것을 특징으로 하는 에이직화한 디지탈 클럭손실 검출기.5. The digital clock loss detector according to claim 4, wherein the division means (210) of the clock calculator (200) is a D flip flop. 제4항에 있어서, 상기 클럭 연산기(200)의 상기 카운터 수단(220)은 16진 카운터인 것을 특징으로 하는 에이직화한 디지탈 클럭손실 검출기.5. The digital clock loss detector of claim 4, wherein the counter means (220) of the clock calculator (200) is a hexadecimal counter. 제4항에 있어서, 상기 클럭손실 판정기(300)의 판정수단(310)은 D플립플럽인 것을 특징으로 하는 에이직화한 디지탈 클럭손실 검출기.5. The digital clock loss detector of claim 4, wherein the determination means (310) of the clock loss determiner (300) is a D flip flop. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940008480A 1994-04-22 1994-04-22 Asic circuit for digital clock loss detection KR960010912B1 (en)

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Application Number Priority Date Filing Date Title
KR1019940008480A KR960010912B1 (en) 1994-04-22 1994-04-22 Asic circuit for digital clock loss detection

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Application Number Priority Date Filing Date Title
KR1019940008480A KR960010912B1 (en) 1994-04-22 1994-04-22 Asic circuit for digital clock loss detection

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KR950029903A true KR950029903A (en) 1995-11-24
KR960010912B1 KR960010912B1 (en) 1996-08-13

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