KR950028551A - Bus selector of exchange - Google Patents

Bus selector of exchange Download PDF

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Publication number
KR950028551A
KR950028551A KR1019940004239A KR19940004239A KR950028551A KR 950028551 A KR950028551 A KR 950028551A KR 1019940004239 A KR1019940004239 A KR 1019940004239A KR 19940004239 A KR19940004239 A KR 19940004239A KR 950028551 A KR950028551 A KR 950028551A
Authority
KR
South Korea
Prior art keywords
bus
signal
selector
output
selecting
Prior art date
Application number
KR1019940004239A
Other languages
Korean (ko)
Other versions
KR970011438B1 (en
Inventor
이진호
Original Assignee
박성규
대우통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 박성규, 대우통신 주식회사 filed Critical 박성규
Priority to KR1019940004239A priority Critical patent/KR970011438B1/en
Publication of KR950028551A publication Critical patent/KR950028551A/en
Application granted granted Critical
Publication of KR970011438B1 publication Critical patent/KR970011438B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q1/00—Details of selecting apparatus or arrangements
    • H04Q1/18—Electrical details
    • H04Q1/30—Signalling arrangements; Manipulation of signalling currents

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

본 발명은 하드웨어적으로 TD－BUS를 선택하기에 적합한 교환기의 버스 선택장치에 관한 것으로，종래에는 TDX－1B 교환기에서 디바이스 버스에 대한 선택을 T－스위치로 선택하기 때문에 스탠바이파워 오프 후 온할 경우，버스 선택의 장애가 발생하여 단방향 통신 및 잡음 등의 문제점이 발생하므로써 이러한 통화 품질 문제점은 T－스위치를 인위적으로 조작하므로 통화 장애를 발생시키거나 SNP에 의해 T－스위치의 C－메모리 온－라인 테스트 잡이 완료될 때까지 약 30분정도 소요되는 결점이 있었으나，본 발명에서는 TD－BUS 신호 선택시，버스 선택부(16)와 버스 선택 신호 출력부(19)를 실현하여 TD－BUS 신호를 하드웨어적으로 처리함으로써 액티브 프로세서 전환시나 소프트웨어에서 발생할 수 있는 서비스 중단을 방지하므로 상기 결점을 개선시킬수 있는 것이다．The present invention relates to a bus selector of an exchange suitable for selecting a TD-BUS in hardware. In the past, when a T-switch selects a device bus selection from a TDX-1B exchanger, when it is turned on after standby power-off, This call quality problem is caused by artificially operating the T-switch due to the failure of bus selection and the problem of unidirectional communication and noise. Although it took about 30 minutes to complete, the present invention realizes the bus selector 16 and the bus selector signal output unit 19 in hardware selection of the TD-BUS signal when the TD-BUS signal is selected. This prevents service interruptions that may occur during active processor transitions or in software, thereby improving the above drawbacks. That will.

Description

교환기의 버스 선택 장치Bus selector of exchange

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명 TDX－1B 교환기의 TD－BUS 선택장치의 일실시예를 나타낸 회로도．3 is a circuit diagram showing an embodiment of a TD-BUS selector of the TDX-1B switch of the present invention.

Claims (3)

/APIF 신호，XTB－SEL 신호 그리고 PROLOC 신호를 인가 받아 디바이스 버스를 선택하기 위한 버스 선택부(16)；상기 버스 선택부(16)의 신호 및 /APIF 신호를 인가 받아 디바이스 버스를 선택하기 위한 TB－SEL 신호를 출력하는 버스 선택신호 출력부(19)를 포함하여 이루어지는 교환기의 버스 선택 장치．Bus selector 16 for selecting a device bus by receiving the / APIF signal, the XTB-SEL signal and the PROLOC signal; TB for selecting the device bus by receiving the signal of the bus selecting section 16 and the / APIF signal A bus selector for an exchange comprising a bus select signal output section (19) for outputting a -SEL signal. 제1항에 있어서，상기 버스 선택부(16)는 XTB－SEL 그리고 PROLOC 신호를 논리합 연산하는 논리합회로(12)와；상기 PROLOC 신호를 인버팅하는 인버터(13)와; 상기 인버터(13)의 출력 및 /APIF 신호 그리고 XTB－SEL 신호를 논리합 연산하는 논리합 회로(14)와；상기 논리합 회로(12，14)의 출력을 논리곱 연산하는 논리곱 회로(15)를 포함하여 이루어지는 교환기의 버스 선택 장치．The bus selecting unit (16) according to claim 1, further comprising: a logic sum circuit (12) for ORing the XTB-SEL and the PROLOC signal; an inverter (13) for inverting the PROLOC signal; A logical sum circuit 14 for performing an OR operation on the output of the inverter 13 and an / APIF signal and an XTB-SEL signal; and an AND product circuit 15 for performing an AND operation on the output of the OR circuits 12 and 14. Bus selector of switchboard. 제1항에 있어서，상기 버스 선택 신호 출력부(19)는 /APIF 신호를 인가 받아 인버팅하는 인버터(17)와；상기 인버터(17)의 출력 및 선택부(16)의 출력을 논리곱 연산하는 논리곱 회로(18)를 포함하여 이루어지는 교환기의 버스 선택 장치．According to claim 1, The bus select signal output unit 19 and the inverter 17 for receiving the / APIF signal inverted; Logic product of the output of the inverter 17 and the output of the selection unit 16; A bus selector for an exchange comprising an AND circuit (18). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940004239A 1994-03-04 1994-03-04 Apparatus for selecting a communication line between a processor and a device in an exchanger KR970011438B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940004239A KR970011438B1 (en) 1994-03-04 1994-03-04 Apparatus for selecting a communication line between a processor and a device in an exchanger

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940004239A KR970011438B1 (en) 1994-03-04 1994-03-04 Apparatus for selecting a communication line between a processor and a device in an exchanger

Publications (2)

Publication Number Publication Date
KR950028551A true KR950028551A (en) 1995-10-18
KR970011438B1 KR970011438B1 (en) 1997-07-10

Family

ID=19378371

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940004239A KR970011438B1 (en) 1994-03-04 1994-03-04 Apparatus for selecting a communication line between a processor and a device in an exchanger

Country Status (1)

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KR (1) KR970011438B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9165612B2 (en) 2013-08-13 2015-10-20 SK Hynix Inc. Memory and memory system including the same
US9361953B2 (en) 2013-08-14 2016-06-07 SK Hynix Inc. Memory and memory system including the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9165612B2 (en) 2013-08-13 2015-10-20 SK Hynix Inc. Memory and memory system including the same
US9361953B2 (en) 2013-08-14 2016-06-07 SK Hynix Inc. Memory and memory system including the same

Also Published As

Publication number Publication date
KR970011438B1 (en) 1997-07-10

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