KR940012124A - Interrupt Vector Processing Circuit - Google Patents
Interrupt Vector Processing Circuit Download PDFInfo
- Publication number
- KR940012124A KR940012124A KR1019920020691A KR920020691A KR940012124A KR 940012124 A KR940012124 A KR 940012124A KR 1019920020691 A KR1019920020691 A KR 1019920020691A KR 920020691 A KR920020691 A KR 920020691A KR 940012124 A KR940012124 A KR 940012124A
- Authority
- KR
- South Korea
- Prior art keywords
- interrupt
- vector
- processing
- responder
- processing circuit
- Prior art date
Links
Abstract
본 발명은 콤퓨터 시스템의 인터럽트 벡터 처리에 관한 것으로, 일반적으로 사용되고 있는 인터럽트 처리회로는 벡터를 사용하는 인터럽트가 자신의 인터럽트 요청의 상태를 데이타 라인상에 벡터 값으로 전달하여도 인터럽트 응답기가 인터럽트 모드를 지원하지 않는 경우에는 그 벡터값이 무시되어지고 인터럽트 응답기는 현재의 인터럽트의 원인을 알기 위하여 인터럽트 소스의 특정 제지스터를 읽는 등의 추가적인 동작을 필요로 하는 문제점을 가지고 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to interrupt vector processing of a computer system. In general, interrupt processing circuits that are generally used include an interrupt responder in interrupt mode even if an interrupt using a vector conveys the status of its interrupt request as a vector value on a data line. If not supported, the vector value is ignored and the interrupt responder has additional problems such as reading a specific register of the interrupt source to determine the cause of the current interrupt.
이에 따라서 본 발명의 목적은 상기와 같은 종래의 인터럽트 장치에 따른 결함을 해결하기 위하여, 인터럽트 처리 로직에 벡터를 처리할 수 있는 팔(PAL : Programmable Array Logic)회로를 추가하여 인터럽트 모드를 지원하지 않는 장치에서도 인터럽트 벡터를 처리할 수 있는 인터럽트 벡터 처리회로를 제공하는데 있다.Accordingly, an object of the present invention does not support interrupt mode by adding a PAL (Programmable Array Logic) circuit capable of processing a vector to the interrupt processing logic in order to solve the defects according to the conventional interrupt apparatus as described above. An apparatus also provides an interrupt vector processing circuit that can process an interrupt vector.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제3도는 본 발명의 인터럽트 백테 처리회로도,3 is an interrupt back processing circuit diagram of the present invention;
제4도는 제3도의 일 실시를 보인 예시도.4 is an exemplary view showing one embodiment of FIG.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920020691A KR940012124A (en) | 1992-11-05 | 1992-11-05 | Interrupt Vector Processing Circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920020691A KR940012124A (en) | 1992-11-05 | 1992-11-05 | Interrupt Vector Processing Circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
KR940012124A true KR940012124A (en) | 1994-06-22 |
Family
ID=67210626
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920020691A KR940012124A (en) | 1992-11-05 | 1992-11-05 | Interrupt Vector Processing Circuit |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR940012124A (en) |
-
1992
- 1992-11-05 KR KR1019920020691A patent/KR940012124A/en not_active Application Discontinuation
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Legal Events
Date | Code | Title | Description |
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WITN | Withdrawal due to no request for examination |