KR950026141A - Symbol timing compensation device - Google Patents

Abstract

The present invention relates to the compensation of symbol timing errors due to multiple phases by multiple paths in the receiver of digital communications. The most common early / rate-gate synchronization timing recovery circuit consists of a sampler, an early accumulator, a rate accumulator, an adder, a loop filter, and a voltage controlled generator. However, such a timing recovery circuit has a problem in that a multipath occurs on a channel, and thus, multiple phases cause the sampling clock phase to not find the correct symbol timing. Therefore, in the present invention, the symbol timing error compensating apparatus is composed of a sampling means, a channel equalizing means, a phase error compensating means, and a timing recovering means to compensate for the phase error of the sampling clock due to multiple images. In the digital communication, if the symbol timing of the receiver has an error, an error rate is increased when determining data. In particular, in order to maximize the channel efficiency, the error rate in data determination is compensated by compensating for error in the symbol timing of the receiver due to the multi-phase due to the multipath in a system such as a high-definition television (HDTV) or a mobile communication that transmits with a higher bit rate per symbol. There is an effect that can be lowered.

Description

Symbol timing compensation device

Since this is an open matter, no full text was included.

4 is a symbol timing compensation circuit diagram according to the present invention.

5 is a detailed block diagram of a phase error compensator according to the present invention.

Claims (2)

Sampling means for sampling a baseband demodulated signal with a sampling clock to output a sampled baseband signal, and a channel for outputting filter coefficient values that are information about the position and magnitude of a multi-phase by inputting the sampled baseband signal. An equalization means, a phase error compensation number for receiving an output signal of the channel equalization means and outputting a symbol timing error compensation signal by multiple phases, and receiving the sampled baseband signal to generate a clock synchronized with symbol timing; Comprising a timing recovery means for receiving a symbol timing error compensation signal by the multi-phase which is the output signal of the phase error compensation means to shift the phase of the clock according to this signal to compensate for the error of the sampling clock by the multi-phase Symbol timing compensation device characterized in that. The demultiplexer of claim 1, wherein the phase error compensating unit receives a filter coefficient value, which is an output signal of a channel equalizer, and separates each symbol period phase to have a sample number of samples per symbol, and a sample number in the demultiplexer. An accumulator unit for accumulating the counter values of the same phase which are disadvantageous, a multiplier unit for receiving the output signals of the remaining accumulators except the accumulator for inputting coefficient values of zero phase, and multiplying them with different weights according to phases, and the multiplier unit An adder for summing all output values of a divider, a divider for dividing the output signal of the adder into an output signal of an accumulator to which the coefficient values of the zero phase are input, a digital-to-analog converter for converting the output signal of the divider into an analog signal; Characterized in that it is composed of a gain controller for receiving the output signal of the digital to analog converter Symbol timing compensation device. ※ Note: The disclosure is based on the initial application.