KR950025541A - Size information generation circuit for data transmission from VME to SBUS - Google Patents

Size information generation circuit for data transmission from VME to SBUS Download PDF

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Publication number
KR950025541A
KR950025541A KR1019940002841A KR19940002841A KR950025541A KR 950025541 A KR950025541 A KR 950025541A KR 1019940002841 A KR1019940002841 A KR 1019940002841A KR 19940002841 A KR19940002841 A KR 19940002841A KR 950025541 A KR950025541 A KR 950025541A
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KR
South Korea
Prior art keywords
vme
sbus
size information
transmission
signal
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Application number
KR1019940002841A
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Korean (ko)
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KR960009668B1 (en
Inventor
윤한록
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이헌조
엘지전자 주식회사
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Priority to KR1019940002841A priority Critical patent/KR960009668B1/en
Publication of KR950025541A publication Critical patent/KR950025541A/en
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Publication of KR960009668B1 publication Critical patent/KR960009668B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Small-Scale Networks (AREA)
  • Information Transfer Systems (AREA)

Abstract

본 발명은 VME 버스와 SBUS를 접속시 데이타 전송 정보에 관한 것으로, 특히 VME버스가 버스 마스터가 되어 SBUS로 데이타 전송시 VME버스상의 데이타 정보를 SBUS의 사이즈(0∼2) 신호를 이용하여 원활한 데이타 전송이 이루어지도록 한 브엠이(VME)를 에스버스(SBUS)로 데이타 전송을 위한사이즈 정보 발생회로에 관한 것이다.The present invention relates to data transfer information when a VME bus and an SBUS are connected. In particular, when the VME bus becomes a bus master and transfers data to the SBUS, the data information on the VME bus is smoothly obtained using the SBUS size (0 to 2) signal. The present invention relates to a size information generating circuit for transferring data from a VME to a SBUS.

이와 같은 본 발명의 목적을 달성하기 위한수단은 VME로부터 출력되는 신호를 버퍼링하는 버퍼수단과, 상기 버퍼수단의 출력 및 VME로부터 의 전송 크기 정보를 입력 받아 SBUS의 전송 데이타 크기 정보 신호를 발생시키는 전송 크기신호 발생수단과, 상기 전송크기 신호 발생수단의 출력을 래치하는 래치수단과, 전송시 버스점유를 요구 신호를 유지시키는 버스 인터페이스 수단으로써 달성되는 것이다.Means for achieving the object of the present invention is a buffer means for buffering the signal output from the VME, and the transmission to generate the transmission data size information signal of the SBUS by receiving the output of the buffer means and the transmission size information from the VME The magnitude signal generating means, the latching means for latching the output of the transmission magnitude signal generating means, and the bus interface means for holding the request signal for bus occupancy during transmission.

Description

브이엠이(VME)를 에스버스(SBUS)로 데이타 전송을 위한 사이즈 정보 발생회로Size information generation circuit for data transmission from VME to SBUS

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명 VME를 SBUS로 데이타 전송을 위한 사이즈 정보 발생회로의 구성도,3 is a configuration diagram of a size information generation circuit for data transmission of the present invention VME to SBUS,

제4도는 제3도의 사이즈 정보 발생부의 PAL 방정식 예시도,4 is an exemplary diagram illustrating a PAL equation of the size information generator of FIG. 3;

제5도는 제3도의 사이즈 정보 발생부의 입출력 신호 타이밍도.5 is an input / output signal timing diagram of the size information generator of FIG.

Claims (2)

VME버스 시스템에서 출력되는 VME AM코드(VME)정보를 입력받아 버퍼링하는 버퍼수단과, 상기 버퍼수단의 출력과 VME사이즈 정보 신호에 따라 논리화하여 SBUS사이즈 정보 신호를 발생하는 사이즈 정보 발생수단과, 상기 사이즈 정보 발생수단의 출력을 래치하는 래치수단과, 상기 래치 수단의 출력을 SBUS와 동기되도록 인터페이스 하는 SBUS인터페이스 수단을 포함하여 이루어진 브이엠이(VME)를 에스버스(SBUS)로 데이타 전송을 위한 사이즈 전보 발생회로.Buffer means for receiving and buffering VME AM code (VME) information output from the VME bus system, size information generating means for generating an SBUS size information signal by logically outputting the buffer means and the VME size information signal; A VME comprising V latches for latching an output of the size information generating means and an SBUS interface means for interfacing the output of the latch means with SBUS for data transmission to the SBUS. Size Telegram Generation Circuit. 제1항에 있어서, 사이즈 정보 발생수단은 VME버스의 AM코드(code)를 입력받아 논리화하여 블록전송을 위한 블록전송 크기 제어신호를 출력하는 블록 전송 사이즈 정보 발생수단과, 입력되는 데이타 스트로브 신호(DOS*)(DSI*) 및 롱워드 신호(LWORD*)를 입력받아 논리화하여 싱글 사이클 전송크기 제어 신호를 출력하는 싱글 싸이클 전송사이즈 정보발생수단으로 이루어짐을 특징으로 한 브이엠이(VME)를 에스버스(SBUS)로 데이타 전송을 위한 사이즈 정보 발생회로.2. The apparatus of claim 1, wherein the size information generating means comprises: block transmission size information generating means for receiving and logically receiving an AM code of a VME bus and outputting a block transfer size control signal for block transmission; and an input data strobe signal. VME characterized by consisting of single cycle transmission size information generating means for receiving (DOS * ) (DSI * ) and long word signal (LWORD * ) and logically outputting a single cycle transmission size control signal. Size information generating circuit for data transmission to SBUS. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940002841A 1994-02-17 1994-02-17 Size information generating circuit for data transfering from vme bus to sbus KR960009668B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940002841A KR960009668B1 (en) 1994-02-17 1994-02-17 Size information generating circuit for data transfering from vme bus to sbus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940002841A KR960009668B1 (en) 1994-02-17 1994-02-17 Size information generating circuit for data transfering from vme bus to sbus

Publications (2)

Publication Number Publication Date
KR950025541A true KR950025541A (en) 1995-09-18
KR960009668B1 KR960009668B1 (en) 1996-07-23

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KR1019940002841A KR960009668B1 (en) 1994-02-17 1994-02-17 Size information generating circuit for data transfering from vme bus to sbus

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KR960009668B1 (en) 1996-07-23

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