KR950022335A

KR950022335A - Data transmission channel switching circuit

Info

Publication number: KR950022335A
Application number: KR1019930027824A
Authority: KR
Inventors: 박형진
Original assignee: 정장호; 금성정보통신 주식회사
Priority date: 1993-12-15
Filing date: 1993-12-15
Publication date: 1995-07-28

Abstract

본 발명은 데이타 송수신 채널 절체회로에 관한 것으로서, HDSL(High-bitrate-Digital Subscriber Line)시스템에 있어서 데이타 송수신 과정중 오류가 발생할 경우 이를 감지하여 다른 채널로 절체시키도록 한 것이다.The present invention relates to a data transmission / reception channel switching circuit, and detects an error during a data transmission / reception process in a high-bitrate-digital subscriber line (HDSL) system to switch to another channel.

이와같은 본 발명의 목적은 각 채널의 송수신 단말기로부터 들어온 해당채널의 신호를 감시하여 해당채널의 동작 오류 여부를 검출하는 각 채널의 모니터링 수단과, 상기 모니터링 수단에서 얻어진 검출값에 따라 다중화 수단에서 출력된 신호를 역다중화 수단으로 궤환시켜줌과 아울러 절체된 채널의 신호를 동기화수단으로 출력하는 각 채널의 스위칭부재와, 상기 모니터링 수단에서 얻어진 검출값에 따라 인터럽트 신호를 입력받고 상기 스위칭부재 및 모니터링 수단을 제어하여 절체선을 통해 채널을 절체하고 각 채널 모두 동작 오류 발생시 사용자에게 이를 알리는 마이크로 프로세서로 이루어지므로써 달성되는 것이다.The object of the present invention as described above is to monitor the signal of the corresponding channel coming from the transmission and reception terminal of each channel, and monitoring means for detecting each channel operation error, and output from the multiplexing means in accordance with the detection value obtained by the monitoring means A switching member of each channel for returning the converted signal to the demultiplexing means and outputting the signal of the switched channel to the synchronization means, and receiving the interrupt signal according to the detected value obtained by the monitoring means. This is achieved by controlling and switching channels through the transfer line, and each channel consists of a microprocessor that notifies the user when an operation error occurs.

Description

Data transmission channel switching circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명 데이타 송수신 채널 절체회로 구성도.2 is a block diagram of a data transmission and reception channel switching circuit of the present invention.

Claims

Monitoring means for each channel to detect whether the operation of the corresponding channel is detected by the signal of the corresponding channel from the transmission and reception terminal of each channel, and the signal output from the multiplexing means in accordance with the detection value obtained by the monitoring means as demultiplexing means. A switching member for each channel that feeds back and outputs a signal of the switched channel to the synchronization means, and receives an interrupt signal according to a detection value obtained by the monitoring means, and controls the switching member and the monitoring means through the switching line. And a microprocessor to notify the user when an operation error occurs in each channel.

The method of claim 1, wherein the monitoring means comprises a pattern generating means for generating a pattern of data by a control signal of a microprocessor retrieving data loss information, and the signal generated by the pattern generating means is fed back through the multiplexing / demultiplexing means. A synchronizing means for synchronizing the received data, a synchronizing means for comparing the synchronizing signal obtained from the synchronizing means obtained from the pattern generating means, and outputting the corresponding interrupt signal to the microprocessor; The first blocking means for bypassing the signal obtained in the normal operation but the blocking (blocking) when switching, and the agent for bypassing or blocking the signal output from the demultiplexing means under the control of the microprocessor. Data comprising two blocking means Reception channel switching circuit.

※ Note: The disclosure is based on the initial application.