KR950021871U - Multiple Synchronous Timing Generation Circuits in Digital Systems - Google Patents
Multiple Synchronous Timing Generation Circuits in Digital SystemsInfo
- Publication number
- KR950021871U KR950021871U KR2019930031887U KR930031887U KR950021871U KR 950021871 U KR950021871 U KR 950021871U KR 2019930031887 U KR2019930031887 U KR 2019930031887U KR 930031887 U KR930031887 U KR 930031887U KR 950021871 U KR950021871 U KR 950021871U
- Authority
- KR
- South Korea
- Prior art keywords
- timing generation
- generation circuits
- digital systems
- synchronous timing
- multiple synchronous
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0095—Arrangements for synchronising receiver with transmitter with mechanical means
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019930031887U KR0125210Y1 (en) | 1993-12-31 | 1993-12-31 | Circuit for generating multiple synchronization timing in digital system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019930031887U KR0125210Y1 (en) | 1993-12-31 | 1993-12-31 | Circuit for generating multiple synchronization timing in digital system |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950021871U true KR950021871U (en) | 1995-07-28 |
KR0125210Y1 KR0125210Y1 (en) | 1998-10-01 |
Family
ID=19374805
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR2019930031887U KR0125210Y1 (en) | 1993-12-31 | 1993-12-31 | Circuit for generating multiple synchronization timing in digital system |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0125210Y1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100343929B1 (en) * | 1999-12-01 | 2002-07-20 | 주식회사 하이닉스반도체 | Apparatus for monitoring reference clock |
KR100342567B1 (en) * | 1999-12-30 | 2002-07-04 | 윤종용 | Optical cross-connect device with transparency |
-
1993
- 1993-12-31 KR KR2019930031887U patent/KR0125210Y1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0125210Y1 (en) | 1998-10-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
N231 | Notification of change of applicant | ||
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
REGI | Registration of establishment | ||
FPAY | Annual fee payment |
Payment date: 20010423 Year of fee payment: 4 |
|
LAPS | Lapse due to unpaid annual fee |