KR950020042A

KR950020042A - High-Speed Digital Data Output Without Phase-Locked Loop

Info

Publication number: KR950020042A
Application number: KR1019930030553A
Authority: KR
Inventors: 한찬호
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1993-12-29
Filing date: 1993-12-29
Publication date: 1995-07-24

Abstract

본 발명은 고속의 외부클럭(clock)에 동기시켜 데이터를 출력하는 시스템이 없어서, 특히 위상 동기 루프가 커버(cover)하지 못하는 고주파 영역에서도 안정적으로 데이타를 출력할 수 있도록 한 위상 동기 루프를 사용하지 않은 고속 디지탈 데이타 출력 장치에 관한 것으로, 종래의 고속직렬 데이타의 출력은 바이트 단위의 시작점을 알지못하고 정확한 트리거 포인트와 테스트 장비의 메모리가 많지 않기 때문에 영상 데이타와 같은 방대한 양의 고속 직결 데이타의 출력을 확인하기에는 어려운 점이 많으며, 위상 동기 루프를 고주파에서 사용할 경우 동기가 되지 않는 경우가 많이 생겨 데이타를 잃어 버리는 경우가 많이 생기게 되는 문제점이 있었다.In the present invention, there is no system for outputting data in synchronization with a high speed external clock, and in particular, a phase-locked loop that can stably output data even in a high frequency region that the phase-locked loop cannot cover is used. A high-speed digital data output device, which is a conventional high-speed serial data output device, does not know the starting point of a byte unit and outputs a large amount of high-speed direct data such as video data because the accurate trigger point and the test equipment do not have much memory. There are many difficulties to confirm, and there is a problem in that the data is lost when the phase locked loop is used at a high frequency.

본 발명은 이와같은 종래의 문제점을 감안하여, 위상 동기 루프를 사용하지 않고 단순히 외부의 클럭을 버퍼만 거쳐 정형하여 데이타의 출력과 외부 클럭간의 위상을 일치시키고, 데이타의 안정성과 신뢰성을 확보하며, 고속직렬 데이타의 출력 확인을 용이하게 하기 위하여 고속직렬 데이타의 병렬 출력을 가능하도록 하여 테스트를 용이하게 한 것이다.In view of such a conventional problem, the present invention does not use a phase-locked loop, but simply forms an external clock through a buffer to match the phase between the output of the data and the external clock, and ensures stability and reliability of the data. In order to facilitate checking the output of the high speed serial data, the parallel output of the high speed serial data is enabled to facilitate the test.

Description

High-Speed Digital Data Output Without Phase-Locked Loop

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래 디지탈 데이타 출력 장치의 구성도,1 is a configuration diagram of a conventional digital data output device,

제2도는 본 발명 위상 동기 루프를 사용하지 않은 고속 디지탈 데이타 출력 장치의 구성도,2 is a block diagram of a fast digital data output device using no phase locked loop of the present invention;

제3도는 제2도의 읽기 요청기에 대한 상세 구성도이다.FIG. 3 is a detailed configuration diagram of the read requester of FIG.

Claims

A buffer 1 for storing 32-bit data Data input by a read signal Read; A mode determiner (2) for determining a high speed data serial output or a high speed data parallel output by mode input; A high speed serial output unit 3 for storing data when the values of the method determiner 2 and the first counter are 31 and outputting data in high speed serial according to the method determiner 2; A first counter (4) for counting a clock (EXS-CLK) input externally for serial output to determine the time stored in said high speed serial output (3); A second counter 5 for counting a clock EXS-CLK inputted for parallel output to determine a time stored in the high speed parallel output 6; A high speed parallel output unit (6) for storing data when the values of the method determiner (2) and the second counter (4W5) are 3 and outputting the data in high speed parallel according to the method determiner (2); A buffer 9 for shaping a read requester 7 for generating a read request signal RR with the first and second counters 4 and 5 and an externally input clock EXP-CLK for serial output; Wow; A high speed digital data output device without a phase locked loop, characterized by a buffer (9) for shaping an externally input clock (EXS-CLK) for parallel output.

2. The read requester (7) according to claim 1, further comprising: an OR gate (7A) for ORing the first coefficient value (C1) and the second coefficient value (C2); And a de-flip-flop (7B) for outputting the output of the OR gate (7A) to the read signal (RR) as an enable signal.

※ Note: The disclosure is based on the initial application.