KR950016093A - Switch Circuit in Closed Loop Network - Google Patents

Switch Circuit in Closed Loop Network Download PDF

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Publication number
KR950016093A
KR950016093A KR1019930024274A KR930024274A KR950016093A KR 950016093 A KR950016093 A KR 950016093A KR 1019930024274 A KR1019930024274 A KR 1019930024274A KR 930024274 A KR930024274 A KR 930024274A KR 950016093 A KR950016093 A KR 950016093A
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KR
South Korea
Prior art keywords
data
signal
buffer
command
detection signal
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KR1019930024274A
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Korean (ko)
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KR100207619B1 (en
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전영진
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김광호
삼성전자 주식회사
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Priority to KR1019930024274A priority Critical patent/KR100207619B1/en
Publication of KR950016093A publication Critical patent/KR950016093A/en
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/90Buffering arrangements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42Loop networks
    • H04L12/427Loop networks with decentralised control
    • H04L12/43Loop networks with decentralised control with synchronous transmission, e.g. time division multiplex [TDM], slotted rings
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/10Packet switching elements characterised by the switching fabric construction
    • H04L49/112Switch control, e.g. arbitration
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/30Peripheral units, e.g. input or output ports

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Small-Scale Networks (AREA)

Abstract

본 발명에 따른 페루프통신망에서의 스위치회로는 트랜시버에서 데이터검출신호를 이용하여 데이터 스트림의 경로를 제어함으로써, 불필요한 데이터 스트림의 전송을 막고 또는 데이터 지연을 막을 수 있는 이점이 있다. 특히 복수개의 입출력포트를 구비하여 LAN(Local Area Network)의 버스와 복수의 DTE와의 연결을 허용하는 장치인 집중기(Concentrator)등에 유효하게 적용할 수 있다.The switch circuit in the Peruvian communication network according to the present invention has an advantage of preventing unnecessary data stream transmission or data delay by controlling the path of the data stream using the data detection signal in the transceiver. In particular, the present invention can be effectively applied to a concentrator, which is a device having a plurality of input / output ports and allowing a connection between a local area network (LAN) bus and a plurality of DTEs.

Description

페루프통신망에서의 스위치회로Switch circuit in the Peruvian communication network

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명이 적용되는 페루프 통신망의 개요도.1 is a schematic diagram of a Peruvian communication network to which the present invention is applied.

Claims (4)

데이터를 단말장치들로 입력하기 위한 입력포트와, 단말장치들로부터의 데이터를 출력하기 위한 출력포트와, 각각의 단말장치의 데이터 송수신을 제어하는 트랜시버와, 입력포트 또는 전단의 스위치수단과 트랜시버로부터 데이터를 입력하기 위한 전송로를 접속하고 트랜시버와 이어지는 스위치수단과 출력포트로 데이터를 출력하기 위한 전송로를 접속하여 단말장치를 루프에서 격리시키거나 또는 접속시키는 것을 제어하기 위한 스위치수단을 각 단말장치마다 구비한 페루프 통신망에 있어서, 상기 스위치수단이 각 전송로들을 연결하기 위해 게이팅하는 버퍼수단; 각 단말장치를 격리 또는 접속하고자 하는 사용자의 커맨드신호와, 격리 또는 접속하고자 하는 단말장치와 접속된 트랜시버의 제1데이터 검출신호와, 이어지는 스위치수단들에서 출력되는 제2데이터 검출 신호에 의해 상기 각 버퍼들을 제어하기 위한 신호와 앞단의 스위치수단에 입력하기 위한 제3데이타검출신호를 출력하는 데이터버퍼제어수단으로 구성된 것을 특징으로 하는 페루프통신망에서의 스위치회로.From an input port for inputting data to the terminal devices, an output port for outputting data from the terminal devices, a transceiver for controlling data transmission and reception of each terminal device, from the input port or the front end switch means and transceiver Each terminal device has a switch means for controlling the isolation or connection of the terminal device from the loop by connecting a transmission path for inputting data, connecting switch means connected to the transceiver, and a transmission path for outputting data to the output port. In the peruvian communication network provided every time, the switch means buffer means for gating to connect the respective transmission paths; The command signal of the user who is to isolate or access each terminal device, the first data detection signal of a transceiver connected to the terminal device to be isolated or connected, and the second data detection signal output from subsequent switch means And a data buffer control means for outputting a signal for controlling the buffers and a third data detection signal for input to the preceding switch means. 제1항에 있어서, 상기 버퍼수단이 전단의 스위치수단으로부터 데이터를 입력하여 출력포트로 데이터를 출력하는 제1버퍼; 전단의 스위치수단으로부터 데이터를 입력하여 이어지는 스위치수단으로 데이터를 출력하는 제2버퍼; 전단의 스위치수단으로부터 데이터를 입력하여 트랜시버로 데이터를 출력하는 제3버퍼; 상기 트랜시버에서의 데이터를 입력하여 상기 트랜시버로 데이터를 출력하는 제4버퍼; 상기 트랜시버에서의 데이터를 입력하여 출력포트로 데이터를 출력하는 제5버퍼; 상기 트랜시버에서의 데이터를 입력하여 이어지는 스위치수단으로 데이터를 출력하기 위한 제6버퍼로 구성됨을 특징으로 하는 페루프통신망에서의 스위치회로.The apparatus of claim 1, wherein the buffer means comprises: a first buffer configured to output data to an output port by inputting data from a switch means of a front end; A second buffer for inputting data from the preceding switch means and outputting the data to the subsequent switch means; A third buffer for inputting data from the switch means of the front end and outputting data to the transceiver; A fourth buffer configured to input data from the transceiver and output data to the transceiver; A fifth buffer configured to output data to an output port by inputting data from the transceiver; And a sixth buffer for inputting data from the transceiver and outputting data to subsequent switching means. 제2항에 있어서, 상기 사용자 커맨드신호가 제1커맨드신호와 제2커맨드신호로 구성됨을 특징으로 하는 페루프통신망에서의 스위치회로.3. The switch circuit of claim 2, wherein the user command signal comprises a first command signal and a second command signal. 제3항에 있어서, 상기 버퍼제어수단이 상기 제1데이터 검출신호와 상기 제2커맨드의 역신호와의 논리곱과, 상기 제2데이터 검출신호와 상기 제1커맨드의 역신호와의 논리곱과 NOR논리연산에 의해 제1버퍼를 액티브로(active low)로 제어하기 위한 제2제어신호를 출력하고, 상기 제1데이터 검출신호와 상기 제2커맨드의 역신호와의 논리곱과, 제2데이타 검출신호와, 제1커맨드의 역신호와의 NAND논리 연산에 의해 제2버퍼를 액티브 로(active low)로 제어하기 위한 제3제어신호를 출력하고, 상기 제1데이터 검출신호와 제2커맨드의 역신호와 NAND 논리곱에 의해 제3버퍼를 액티브 로(active low)로 제어하기 위한 제3제어신호를 출력하고, 상기 제1데이타 검출신호의 역신호와 상기 제2커맨드신호와의 NOR논리연산에 의해 제4버퍼를 액티브로(active low)로 제어하기 위한 제4제어신호를 출력하고, 상기 제2데이터 검출신호와 상기 제1커맨드의 역신호와의 논리곱과, 상기 제1데이터 검출신호와, 상기 제2커맨드이 역신호와의 NAND논리연산에 의해 제5버퍼를 액티브 로(active low)로 제어하기 위한 제5제어신호를 출력하고, 상기 제1데이터 검출신호와 상기 제2데이터 검출신호와 상기 제1커맨드의 역신호와 상기 제2커맨드의 역신호와의 NAND논리연산에 의해 제6버퍼를 액트브 로(active low)로 제어하기 위한 제6제어신호를 출력하고, 상기 제1데이터 검출신호와 상기 제2데이터 검출신호와의 OR논리연산에 의해 상기 제3데이터 검출신호를 출력하는 것을 특징으로 하는 페루프통신망에서의 스위치회로.4. The apparatus of claim 3, wherein the buffer control means comprises: a logical product of the first data detection signal and an inverse signal of the second command, a logical product of the second data detection signal and the inverse signal of the first command, A second control signal for controlling the first buffer to be active low by NOR logic operation is output, and the logical product of the first data detection signal and the inverse signal of the second command, and the second data A third control signal for controlling the second buffer to be active low by NAND logic operation of the detection signal and the inverse signal of the first command, and outputting a third control signal of the first data detection signal and the second command. A third control signal for controlling the third buffer to be active low by the inverse signal and the NAND logical product, and NOR logic operation of the inverse signal of the first data detection signal and the second command signal The fourth buffer for controlling the fourth buffer to be active low by A fifth buffer is output by outputting an audio signal and performing a NAND logic operation on the logical product of the second data detection signal and the inverse signal of the first command, the first data detection signal, and the second command to the inverse signal. Outputs a fifth control signal for controlling the active low; and converts the first data detection signal, the second data detection signal, the inverse signal of the first command, and the inverse signal of the second command. Outputting a sixth control signal for controlling the sixth buffer to active low by NAND logic operation, and performing the OR logic operation of the first and second data detection signals 3. A switch circuit in a Peruvian communication network, characterized by outputting a data detection signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930024274A 1993-11-16 1993-11-16 Switching circuits in closed loop communication system KR100207619B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930024274A KR100207619B1 (en) 1993-11-16 1993-11-16 Switching circuits in closed loop communication system

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Application Number Priority Date Filing Date Title
KR1019930024274A KR100207619B1 (en) 1993-11-16 1993-11-16 Switching circuits in closed loop communication system

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KR950016093A true KR950016093A (en) 1995-06-17
KR100207619B1 KR100207619B1 (en) 1999-07-15

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