KR950015852U - Negative OR circuit - Google Patents
Negative OR circuitInfo
- Publication number
- KR950015852U KR950015852U KR2019930022973U KR930022973U KR950015852U KR 950015852 U KR950015852 U KR 950015852U KR 2019930022973 U KR2019930022973 U KR 2019930022973U KR 930022973 U KR930022973 U KR 930022973U KR 950015852 U KR950015852 U KR 950015852U
- Authority
- KR
- South Korea
- Prior art keywords
- negative
- circuit
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019930022973U KR960000052Y1 (en) | 1993-11-04 | 1993-11-04 | Exclusive or circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019930022973U KR960000052Y1 (en) | 1993-11-04 | 1993-11-04 | Exclusive or circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950015852U true KR950015852U (en) | 1995-06-19 |
KR960000052Y1 KR960000052Y1 (en) | 1996-01-04 |
Family
ID=19367095
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR2019930022973U KR960000052Y1 (en) | 1993-11-04 | 1993-11-04 | Exclusive or circuit |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR960000052Y1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100748359B1 (en) * | 2006-08-08 | 2007-08-09 | 삼성에스디아이 주식회사 | Logic gate, scan driver and organic light emitting display using the same |
-
1993
- 1993-11-04 KR KR2019930022973U patent/KR960000052Y1/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100748359B1 (en) * | 2006-08-08 | 2007-08-09 | 삼성에스디아이 주식회사 | Logic gate, scan driver and organic light emitting display using the same |
Also Published As
Publication number | Publication date |
---|---|
KR960000052Y1 (en) | 1996-01-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
REGI | Registration of establishment | ||
FPAY | Annual fee payment |
Payment date: 19981231 Year of fee payment: 4 |
|
LAPS | Lapse due to unpaid annual fee |