KR950015801A - Structure of Thin Film Transistor - Google Patents

Structure of Thin Film Transistor Download PDF

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Publication number
KR950015801A
KR950015801A KR1019930023720A KR930023720A KR950015801A KR 950015801 A KR950015801 A KR 950015801A KR 1019930023720 A KR1019930023720 A KR 1019930023720A KR 930023720 A KR930023720 A KR 930023720A KR 950015801 A KR950015801 A KR 950015801A
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KR
South Korea
Prior art keywords
region
source
active layer
thin film
film transistor
Prior art date
Application number
KR1019930023720A
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Korean (ko)
Inventor
양명수
Original Assignee
이헌조
주식회사 엘지전자
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Publication date
Application filed by 이헌조, 주식회사 엘지전자 filed Critical 이헌조
Priority to KR1019930023720A priority Critical patent/KR950015801A/en
Publication of KR950015801A publication Critical patent/KR950015801A/en

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Abstract

본 발명은 박막트랜지스터의 구조에 관한것으로, 박막트랜지스터의 차단전류는 낮추되 온 전류가 감소되지 않도록 LDD영역을 형성함에 있어 종래기술에서 미스 얼라인(Allign)에 의해 발생되는 소오스 및 드레인의 영역폭변화를 방지하기 위해 버퍼층의 선택영역을 테이퍼 에치하여 리세스영역을 형성한 후, 리세스영역에 걸쳐 일정폭을 갖는 활성층을 형성하고 게이트절연막을 형성한 다음 리세스영역의 양측경사부분의 일정부분에 걸쳐 게이트를 형성한다. 이어 이온주입공정을 실시하여 활성층중 평면부분에는 고농도의 불순물이 주입되어 소오스 및 드레인영역이 형성되고, 경사진부분에는 LDD영역이 동시에 형성되도록하여 미스 얼라인의 문제점이 해소되고 공정의 단순화가 이루어진다.The present invention relates to a structure of a thin film transistor, wherein the blocking current of the thin film transistor is lowered, but in forming the LDD region so that the on-current is not reduced, the source and drain regions of the source and drain generated by misalignment in the prior art. In order to prevent the change, the recessed region is formed by tapering the selected region of the buffer layer, and then an active layer having a predetermined width is formed over the recessed region, a gate insulating film is formed, and a predetermined portion of both inclined portions of the recessed region Form a gate over. Subsequently, a high concentration of impurities are implanted into the planar portion of the active layer to form a source and a drain region, and an LDD region is formed simultaneously on the inclined portion to solve the problem of misalignment and simplify the process. .

Description

박막트랜지스터의 구조Structure of Thin Film Transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도(A) 내지 (B)는 본 발명의 박막트랜지스터 공정단면도,2 (A) to (B) is a cross-sectional view of the thin film transistor process of the present invention,

제3도는 제2도의 경사부분확대도.3 is an enlarged view of the inclined portion of FIG.

Claims (2)

절연기판(1)상에 형성되는 절연물로서 선택영역에 리세스영역이 형성된 버퍼층(7)과, 상기 버퍼층(2)상에서 리세스영역에 걸쳐, 리세스영역보다 넓은폭으로 형성되는 활성층(3)과, 상기 활성층(3)의 선택영역을 제외한 전표면상에 형성되는 게이트 절연막(4)과 상기 게이트절연막(4) 중 리세스영역의 일측경사부분과 타측부분의 하단에 걸쳐 형성되는 게이트(5)와, 상기 활성층(3)중 게이트(9 형성부분 이외의 평면부분에 형성되는 소오스 및 드레인영역(6)과, 상기 활성층(3)중 경사부분에 형성되는 LDD영역(7)과, 상기 소오스 및 드레인영역(6)의 일정폭을 제외한 전표면상에 형성되는 절연막(8)과, 상기 소오스및 드레인영역(6)에 접하여 층간절연막(8) 상에서 일정폭으로 형성되는 소오스 및 드레인전극(9)으로 구성됨을 특징으로 하는 박막트랜지스터의 구조.A buffer layer 7 having a recessed region in a selected region as an insulator formed on the insulating substrate 1, and an active layer 3 formed wider than the recessed region over the recessed region on the buffer layer 2. And a gate insulating film 4 formed on the entire surface except for the selected region of the active layer 3, and a gate 5 formed over one of the inclined portion of the recess region and the lower end of the other portion of the gate insulating film 4; Source and drain regions 6 formed in planar portions other than the gate 9 forming portions of the active layer 3, LDD regions 7 formed in the inclined portions of the active layer 3, and the source and An insulating film 8 formed on the entire surface except the predetermined width of the drain region 6 and a source and drain electrode 9 formed on the interlayer insulating film 8 in contact with the source and drain regions 6 at a predetermined width. Structure of a thin film transistor, characterized in that configured. 제1항에 있어서, 버퍼층(2)의 리세스영역의 경사부분의 경사각은 20°이상임을특징으로 하는 박막트랜지스터의 구조.The structure of the thin film transistor according to claim 1, wherein the inclination angle of the inclined portion of the recessed region of the buffer layer (2) is 20 degrees or more. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930023720A 1993-11-09 1993-11-09 Structure of Thin Film Transistor KR950015801A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930023720A KR950015801A (en) 1993-11-09 1993-11-09 Structure of Thin Film Transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930023720A KR950015801A (en) 1993-11-09 1993-11-09 Structure of Thin Film Transistor

Publications (1)

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KR950015801A true KR950015801A (en) 1995-06-17

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KR1019930023720A KR950015801A (en) 1993-11-09 1993-11-09 Structure of Thin Film Transistor

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100426688B1 (en) * 2002-01-29 2004-04-13 일진다이아몬드(주) Thin film transistor for liquid crystal display (LCD) and Method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100426688B1 (en) * 2002-01-29 2004-04-13 일진다이아몬드(주) Thin film transistor for liquid crystal display (LCD) and Method of manufacturing the same

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