KR950015731A - Package for semiconductor device and manufacturing method thereof - Google Patents

Package for semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
KR950015731A
KR950015731A KR1019930023492A KR930023492A KR950015731A KR 950015731 A KR950015731 A KR 950015731A KR 1019930023492 A KR1019930023492 A KR 1019930023492A KR 930023492 A KR930023492 A KR 930023492A KR 950015731 A KR950015731 A KR 950015731A
Authority
KR
South Korea
Prior art keywords
package
inner leads
insulator
semiconductor
package body
Prior art date
Application number
KR1019930023492A
Other languages
Korean (ko)
Other versions
KR100296845B1 (en
Inventor
김동국
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019930023492A priority Critical patent/KR100296845B1/en
Publication of KR950015731A publication Critical patent/KR950015731A/en
Application granted granted Critical
Publication of KR100296845B1 publication Critical patent/KR100296845B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

듀얼 타입 또는 쿼드 타입 반도체 장치용 패키지에 있어서, 반도체 장치용 패키지의 외관품질과 반도체 장치용 패키지의 실장시 발생되는 솔더 흡습성을 향상시키기 위하여 인너리드들의 상부에 소정 크기의 절연체를 부착시킨 후, 상기 절연체 상부에 반도체 칩을 실장하는 칩어태치하고, 상기 반도체 칩의 본딩패드와 인너리드들을 전기적 연결수단으로 와이어 본딩하며, 상기 반도체 칩과 본딩된 와이어가 보호되고, 인너리드들의 저면 선단부가 노출되도록 에폭시 몰드 컴파운드로 봉지하여 패키지 몸체를 형성하는 몰딩하고, 상기 몰딩공정에 의해 형성된 패키지 몸체의 측면부에 일정간격을 두고 포켓들을 형성하며, 상기 포켓들의 내부에 아웃터 리드들을 절곡하여 삽입함으로써 반도체 장치용 패키지를 제조한다, 따라서 패키지 몸체의 밑면에 노출되는 인너리드들의 선단부가 반도체 기판에 직접 실장되는 표면 실장형 반도체 패키지에 유용하게 적용된다In a package for a dual type or quad type semiconductor device, in order to improve the appearance quality of the package for the semiconductor device and the solder hygroscopicity generated during the mounting of the package for the semiconductor device, after attaching an insulator of a predetermined size on top of the inner leads, A chip attach for mounting a semiconductor chip on the insulator, wire bonding the bonding pads and the inner leads of the semiconductor chip with electrical connection means, protecting the semiconductor chip and the bonded wires, and exposing the bottom ends of the inner leads. The semiconductor device package is formed by molding a package to form a package body by encapsulating with a mold compound, forming pockets at predetermined intervals on the side surface of the package body formed by the molding process, and bending and inserting the outer leads into the pockets. To the bottom of the package body The tip of exposed inner leads is usefully applied to surface mount semiconductor packages that are directly mounted on a semiconductor substrate.

Description

반도체 장치용 패키지 및 그 제조방법Package for semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제6도는 이 발명에 따른 반도체 장치용 패키지의 일실시예를 나타내는 절단 요부 사시도.6 is a perspective view of a cutting main portion showing an embodiment of a package for a semiconductor device according to the present invention.

Claims (13)

반도체 기판에 실장되는 표면 실장형 반도체 패키지에 있어서, 인너리드들의 상부에 소정 크기의 절연체가 부착되고, 상기 절연체 상부에 반도체 칩이 실장되어 접착되며, 상기 반도체 칩의 본딩패드와 인너리드가 와이어로 본딩된 후, 에폭시 몰드 컴파운드로 몰딩되어 패키지 몸체가 형성되며, 상기 패키지 몸체의 밑면에 수평하게 인너리드들이 절단되어 상기 반도체 패키지의 측면부로 돌출되지 않는 것을 특징으로 하는 반도체 장치용 패키지.In a surface mount semiconductor package mounted on a semiconductor substrate, an insulator of a predetermined size is attached to the inner leads, a semiconductor chip is mounted and bonded to the upper part of the insulator, and a bonding pad and an inner lead of the semiconductor chip are wired. After bonding, the package is molded with an epoxy mold compound to form a package body, the inner leads are cut horizontally on the bottom surface of the package body so as not to protrude to the side portion of the semiconductor package. 제1항에 있어서, 상기 인너리드들의 저면이 상기 패키지 몸체의 밑면에 노출되는 것을 특징으로 하는 반도체 장치용 패키지.The package of claim 1, wherein bottom surfaces of the inner leads are exposed on a bottom surface of the package body. 인너리드들의 상부에 소정크기의 절연체를 부착시킨 후, 상기 절연체 상부에 반도체 칩을 실장하는 칩 어태치 공정과; 상기 반도체 칩의 본딩패드와 인너리드들을 전기적 연결수단으로 본딩하는 와이어 본딩 공정과; 상기 반도체 칩과 본딩된 와이어가 보호되고, 인너리드들의 저면 선단부가 노출되도록 에폭시 몰드 컴파운드로 봉지하여 패키지 몸체를 형성하는 몰딩공정을 구비하여 상기 몰딩공정에 의해 형성된 패키지 몸체의 측면부에 인너리드들이 돌출되지 않는 반도체 장치용 패키지 제조방법.A chip attach process of attaching an insulator of a predetermined size on top of inner leads, and then mounting a semiconductor chip on the insulator; A wire bonding process of bonding the bonding pads and the inner leads of the semiconductor chip with electrical connection means; Inner leads are protruded on the side surface of the package body formed by the molding process by a molding process of protecting the wire bonded to the semiconductor chip and encapsulating with an epoxy mold compound to form a package body so that the bottom ends of the inner leads are exposed. Method for manufacturing a package for a semiconductor device. 제3항에 있어서, 상기 인너리드들의 저면이 상기 패키지 몸체의 밑면에 노출되는 것을 특징으로하는 반도체 장치용 패키지 제조방법.The method of claim 3, wherein the bottom surfaces of the inner leads are exposed on a bottom surface of the package body. 반도체 기판에 실장되는 표면 실장형 반도체 패키지에 있어서, 인너리드들의 상부에 소정크기의 절연체가 부착되고, 상기 절연체 상부에 반도체 칩이 실장되어 접착되며, 상기 반도체 칩의 본딩패드와 인너리드가 전기적 연결수단으로 본딩된 후, 에폭시 몰드 컴파운드로 몰딩되어 패키지 몸체가 형성되며, 몰딩시 형성된 팩키지 몸체 측면부의 포켓들의 내부로 아웃터 리드들이 절곡되어 삽입된 반도체 장치용 패키지.In a surface mount semiconductor package mounted on a semiconductor substrate, an insulator of a predetermined size is attached to the inner leads, a semiconductor chip is mounted and bonded to the upper part of the insulator, and a bonding pad and an inner lead of the semiconductor chip are electrically connected. After bonding by means, molded with an epoxy mold compound to form a package body, wherein the outer lead is bent and inserted into the pockets of the package body side portion formed during molding. 제4항에 있어서, 상기 포켓들 내부에 삽입된 아웃터 리드들은 질곡되어 패키지 몸체의 상부로노출되지 않도록 하는 것을 특징으로 하는 반도체 장치용 패키지.The package of claim 4, wherein the outer leads inserted into the pockets are bent so as not to be exposed to the upper portion of the package body. 인너리드들의 상부에 소정크기의 절연체를 부착시킨 후, 상기 절연체 상부에 반도체 칩을 실장하는 칩 어태치 공정과; 상기 반도체 칩의 본딩패드와 인너리드들을 전기적 연결수단으로 본딩하는 와이어 본딩 공정과; 상기 반도체 칩과 본딩된 와이어가 보호되고, 인너리드들의 저면 선단부가 노출되도록 에폭시 몰드 컴파운드로 봉지하여 패키지 몸체를 형성하는 몰딩공정과; 상기 몰딩공정에 의해 패키지 몸체의 측면부에 일정간격을 두고 형성된 포켓들의 내부에 아웃터 리드들을 절곡하여 삽입하는 공정을 각각 구비하는 반도체 장치용 패키지 제조방법.A chip attach process of attaching an insulator of a predetermined size on top of inner leads, and then mounting a semiconductor chip on the insulator; A wire bonding process of bonding the bonding pads and the inner leads of the semiconductor chip with electrical connection means; A molding step of forming a package body by protecting the wire bonded to the semiconductor chip and encapsulating it with an epoxy mold compound to expose bottom ends of inner leads; And a step of bending and inserting the outer leads into pockets formed at predetermined intervals in the side surface of the package body by the molding process. 제7항에 있어서, 상기 절연체를 인너리드의 끝단에 형성되는 반도체 장치용 패키지 제조방법.8. The method of claim 7, wherein the insulator is formed at an end of the inner lead. 제7항에 있어서, 상기 절연체는 인너리드의 배열이나 반도체 패키지의 형상에 따라 임의의 선택할 수 있도록 일표면을 활용하는 윈도우 형상인 것을 특징으로 하는 반도체 장치용 패키지 제조방법.The method of claim 7, wherein the insulator has a window shape that utilizes one surface to be arbitrarily selected according to the inner lead arrangement or the shape of the semiconductor package. 제7항에 있어서, 상기 절연체는 인너리드의배열이나 반도체 패키지의 형상에 따라 임의의 선택할 수 있도록 분활표면을 활용하는 분활형상인 것을 특징으로 하는 반도체 장치용 패키지 제조방법.The method for manufacturing a package for a semiconductor device according to claim 7, wherein the insulator has a split shape utilizing a split surface so as to be arbitrarily selected according to the arrangement of inner leads or the shape of the semiconductor package. 제7항에 있어서, 상기 인너리드들은 에폭시 몰드 컴파운드와 결합력을 향상시키기 위하여 너치형태 또는 홀형태의 홈을 형성시킨 것을 특징으로 하는 반도체 장치용 패키지 제조방법.The method of claim 7, wherein the inner leads are formed in a groove-shaped or hole-shaped groove in order to improve bonding strength with the epoxy mold compound. 제7항에 있어서, 상기 포켓들은 인접 포켓에 서로 간섭을 주지 않으며 아웃터리드들의 폭보다 넓게 형성하여 에폭시 몰드 컴파운드 성형후 아웃터 리드의 삽입을 원활히 하도록 한 반도체 장치용 패키지 제조방법.The method of claim 7, wherein the pockets are formed to be wider than the width of the outer pockets without interfering with each other in adjacent pockets to facilitate insertion of the outer lead after molding the epoxy mold compound. 제12항에 있어서, 상기 아웃터리드들은 포켓들 측면에 완전히 삽입되거나 외부로 돌출되어 삽입되는 반도체 장치용 패키지 제조방법.The method of claim 12, wherein the outdents are completely inserted into the side surfaces of the pockets or protruded outwardly. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930023492A 1993-11-06 1993-11-06 Semiconductor package and manufacturing method thereof KR100296845B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930023492A KR100296845B1 (en) 1993-11-06 1993-11-06 Semiconductor package and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930023492A KR100296845B1 (en) 1993-11-06 1993-11-06 Semiconductor package and manufacturing method thereof

Publications (2)

Publication Number Publication Date
KR950015731A true KR950015731A (en) 1995-06-17
KR100296845B1 KR100296845B1 (en) 2001-10-24

Family

ID=37528092

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930023492A KR100296845B1 (en) 1993-11-06 1993-11-06 Semiconductor package and manufacturing method thereof

Country Status (1)

Country Link
KR (1) KR100296845B1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100487464B1 (en) * 1997-12-12 2005-08-10 삼성전자주식회사 Semiconductor chip package using lead frame
KR20200065794A (en) 2018-11-30 2020-06-09 주식회사 코위드원 Damage Prevention Sheet for Underground Facilities
KR20200066111A (en) 2018-11-30 2020-06-09 주식회사 코위드원 Underground facility damage prevention sheet and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62123752A (en) * 1985-11-25 1987-06-05 Hitachi Ltd Resin sealed type semiconductor device
JPS63107158A (en) * 1986-10-24 1988-05-12 Hitachi Ltd Manufacture of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100487464B1 (en) * 1997-12-12 2005-08-10 삼성전자주식회사 Semiconductor chip package using lead frame
KR20200065794A (en) 2018-11-30 2020-06-09 주식회사 코위드원 Damage Prevention Sheet for Underground Facilities
KR20200066111A (en) 2018-11-30 2020-06-09 주식회사 코위드원 Underground facility damage prevention sheet and manufacturing method thereof

Also Published As

Publication number Publication date
KR100296845B1 (en) 2001-10-24

Similar Documents

Publication Publication Date Title
KR100214463B1 (en) Lead frame of clip type and method manufacture of the package
US7008824B2 (en) Method of fabricating mounted multiple semiconductor dies in a package
US6437429B1 (en) Semiconductor package with metal pads
US6157074A (en) Lead frame adapted for variable sized devices, semiconductor package with such lead frame and method for using same
KR950030323A (en) Semiconductor device and production method of semiconductor device and semiconductor module
KR960009136A (en) Semiconductor package and manufacturing method
KR950021435A (en) Resin-sealed semiconductor device and manufacturing method thereof
KR19980032479A (en) Surface installation TO-220 package and its manufacturing process
US6427976B1 (en) Lead-frame-based chip-scale package and method of manufacturing the same
KR100252737B1 (en) Resin-sealed semiconductor device and its manufacture
KR950025963A (en) Manufacturing Method of Semiconductor Device
KR950015731A (en) Package for semiconductor device and manufacturing method thereof
KR20080089041A (en) Led package comprising lead frame being without outer lead and method for fabricating the same
KR910000018B1 (en) Semiconductor device using the lead-frame and method of manufacture there of
JP3134445B2 (en) Resin-sealed semiconductor device
KR100206886B1 (en) Culumn type package
KR930014845A (en) VSMP (VERTICAL SMALL MOUNTING PACKAGE) Structure and Manufacturing Method
KR101322452B1 (en) Led package comprising lead frame being without outer lead and method for fabricating the same
KR200169730Y1 (en) Lead frame for semiconductor package
KR200164521Y1 (en) Tl type semiconductor package
KR100267766B1 (en) Variable chip-size applicable package with rivet pin of terminal for connection to outer terminal and method for fabricating the same
KR960000462Y1 (en) Board semiconductor device
KR100867571B1 (en) Case for power semiconductor module and method for manufacturing power semiconductor module using the case
KR970008530A (en) Surface-mount leadframes, semiconductor packages using the same, and manufacturing methods thereof
KR100244502B1 (en) Chip size package

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070418

Year of fee payment: 7

LAPS Lapse due to unpaid annual fee