KR950015605A - Semiconductor device with contact portion having metal wiring - Google Patents

Semiconductor device with contact portion having metal wiring Download PDF

Info

Publication number
KR950015605A
KR950015605A KR1019940031150A KR19940031150A KR950015605A KR 950015605 A KR950015605 A KR 950015605A KR 1019940031150 A KR1019940031150 A KR 1019940031150A KR 19940031150 A KR19940031150 A KR 19940031150A KR 950015605 A KR950015605 A KR 950015605A
Authority
KR
South Korea
Prior art keywords
diffusion layer
metal wiring
contact
semiconductor device
contact portion
Prior art date
Application number
KR1019940031150A
Other languages
Korean (ko)
Other versions
KR0171646B1 (en
Inventor
가오루 나리따
Original Assignee
가네꼬 히사시
니뽄 덴끼 가부시끼 가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가네꼬 히사시, 니뽄 덴끼 가부시끼 가이샤 filed Critical 가네꼬 히사시
Publication of KR950015605A publication Critical patent/KR950015605A/en
Application granted granted Critical
Publication of KR0171646B1 publication Critical patent/KR0171646B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

p형 반도체 기판의 표면상에는 n형 확산층이 형성되어 있고, 상기 확산층은 전기 접속을 위해 층간 절연층을 통해 형성된 접점 홀을 거쳐 알루미늄 배선과 접촉하며, 상기 알루미늄 배선의 접점부 바로 아래에는 n형 확산층보다 높은 불순물 농도를 가지며 접합 깊이가 깊은 접점 n형 확산층이 형성되어 있고, 상기 접점 n형 확산층의 외측은 저 불순물 농도의 n형 벽에 의해 둘러싸여 있으며, 상기 구조는, 얕은 확산층에 접속된 외부 단자에 정전 펄스가 인가되는 경우, 확산층의 접합 파괴를 성공적으로 방지할 수 있다.An n-type diffusion layer is formed on the surface of the p-type semiconductor substrate, and the diffusion layer is in contact with the aluminum wiring via a contact hole formed through an interlayer insulating layer for electrical connection, and an n-type diffusion layer directly under the contact portion of the aluminum wiring. A contact n-type diffusion layer having a higher impurity concentration and a deeper junction depth is formed, and an outer side of the contact n-type diffusion layer is surrounded by an n-type wall of low impurity concentration, and the structure is an external terminal connected to a shallow diffusion layer. In the case where an electrostatic pulse is applied, the junction breakage of the diffusion layer can be prevented successfully.

Description

금속 배선을 갖는 접점부를 구비한 반도체 장치Semiconductor device with contact portion having metal wiring

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 접점부를 갖는 반도체 장치의 제1실시예의 평면도.2 is a plan view of a first embodiment of a semiconductor device having a contact portion according to the present invention;

Claims (7)

금속 배선을 갖는 접점부를 구비한 반도체 장치에 있어서, 제1도전형의 반도체 기판과, 사기 반도체 기판의 표면 영역에 형성된 제2도전형의 제1확산층과, 상기 제1확산층에 접촉하는 급속 배선과, 상기 금속 배선의 접점부 바로 아래에 형성되어 있으며, 상기 제1확산층 보다 높은 불순물 농도와 보다 깊은 접합 깊이를 갖는 제2도전형의 제2확산층과, 상기 제2확산층의 외측에서 제2확산층을 둘러싸도록 형성되어 있으며, 제1확산층 보다 낮은 불순물 농도를 갖은 제2도전형의 제3확산층을 포함하는 것을 특징으로 하는 금속 배선을 갖는 접점부를 구비한 반도체 장치.A semiconductor device having a contact portion having a metal wiring, comprising: a semiconductor substrate of a first conductivity type, a first diffusion layer of a second conductivity type formed in a surface region of a fraudulent semiconductor substrate, and a rapid wiring contacting the first diffusion layer; And a second diffusion layer of a second conductivity type formed under the contact portion of the metal wiring and having a higher impurity concentration and a deeper junction depth than the first diffusion layer, and a second diffusion layer outside the second diffusion layer. And a third diffusion layer of a second conductivity type which is formed so as to surround and has a lower impurity concentration than the first diffusion layer. 제1항에 있어서, 상기 제1확산층의 접촉 깊이는 0.5㎛ 이하인 것을 특징으로 하는 금속 배선을 갖는 접점부를 구비한 반도체 장치.2. The semiconductor device according to claim 1, wherein a contact depth of said first diffusion layer is 0.5 mu m or less. 제2항에 있어서, 상기 제3확산층의 불순물 농도는 한자리 숫자 범위내에서 제l확산층 보다 낮은 것을 특징으로 하는 금속 배선을 갖는 접점부를 구비한 반도체 장치.3. The semiconductor device according to claim 2, wherein the impurity concentration of the third diffusion layer is lower than that of the first diffusion layer within a single digit range. 제1항에 있어서, 상기 금속 배선은 외부 단자에 접속되는 것을 특징으로 하는 금속 배선을 갖는 접점부를 구비한 반도체 장치.The semiconductor device according to claim 1, wherein the metal wiring is connected to an external terminal. 금속 배선과 접촉하는 접촉부를 갖는 반도체 장치에 있어서, 제1도전형의 반도체 기판과, 상기 반도체 기판의 표면에 형성된 소자 분리 산화층과, 상기 소자 분리 산화층의 양측면에 있는 반도체 기판의 표면 영역에 형성된 제2도전형의 한쌍의 제1확산층과, 강기 제1확산층과 접촉하는 금속 배선과, 금속 배선의 접점부 바로 아래에 형성되어 있고, 제1확산층 보다 높은 불순물 농도를 가지며, 제1확은층 보다 깊은 접합 깊이를 갖는 제2도전형의 제2확산층과, 상기 제2확산층의 외측에서 제2확산층을 둘러싸도록 형성되어 있으며 제1착산층 보다 낮은 불순물 농도를 갖는 제2도전형의 제3확산층을 포한하는 것을 특징으로 하는 금속 배선과 접촉하는 접 촉부를 갖는 반조체 장치.A semiconductor device having a contact portion in contact with a metal wiring, comprising: a semiconductor substrate of a first conductivity type, an element isolation oxide layer formed on a surface of the semiconductor substrate, and a surface region of a semiconductor substrate on both sides of the element isolation oxide layer; A pair of two conductive type first diffusion layers, a metal wiring contacting the first rigid diffusion layer, and a metal wiring directly below the contact portion, and have a higher impurity concentration than the first diffusion layer. A second diffusion layer of the second conductivity type having a deep junction depth and a third diffusion layer of the second conductivity type formed to surround the second diffusion layer outside the second diffusion layer and having a lower impurity concentration than the first diffusion layer. Semi-fabricated device having a contact portion in contact with the metal wiring, characterized in that it comprises. 제5항에 있어서, 상기 금속 배선의 한쪽 단자는 접지 배선 (grounding wiring) 또는 전원 배선 (power source wiring)에 접촉되고, 다른쪽 단부는 외부 단자에 접속되는 것을 특징으로 하는 금속 배선과 접촉하는 접촉부를 갖는 반도체 장치.6. The contact portion according to claim 5, wherein one terminal of the metal wiring is connected to a grounding wiring or a power source wiring, and the other end thereof is connected to an external terminal. A semiconductor device having a. 제5항에 있어서, 상기 제1확산층은 소자 분리 산화층과 접촉하고, 제3확산층과 소자 분리 산화층 사이의 거리는 2㎛ 이하인 것을 특징으로 하는 금속 배선과 접촉하는 접촉부를 갖는 반도체 장치.6. The semiconductor device according to claim 5, wherein the first diffusion layer is in contact with the device isolation oxide layer, and the distance between the third diffusion layer and the device isolation oxide layer is 2 µm or less. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940031150A 1993-11-25 1994-11-25 Semiconductor device having a solid metal wiring with a contact portion for improved protection KR0171646B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP5319009A JP2611639B2 (en) 1993-11-25 1993-11-25 Semiconductor device
JP93-319009 1993-11-25

Publications (2)

Publication Number Publication Date
KR950015605A true KR950015605A (en) 1995-06-17
KR0171646B1 KR0171646B1 (en) 1999-03-30

Family

ID=18105487

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940031150A KR0171646B1 (en) 1993-11-25 1994-11-25 Semiconductor device having a solid metal wiring with a contact portion for improved protection

Country Status (3)

Country Link
US (1) US5521413A (en)
JP (1) JP2611639B2 (en)
KR (1) KR0171646B1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5705841A (en) * 1995-12-22 1998-01-06 Winbond Electronics Corporation Electrostatic discharge protection device for integrated circuits and its method for fabrication
KR100211539B1 (en) * 1995-12-29 1999-08-02 김영환 Electrostatic discharge protection device of semiconductor device and manufacture thereof
JP3049001B2 (en) * 1998-02-12 2000-06-05 日本電気アイシーマイコンシステム株式会社 FUSE DEVICE AND ITS MANUFACTURING METHOD
US6355508B1 (en) 1998-09-02 2002-03-12 Micron Technology, Inc. Method for forming electrostatic discharge protection device having a graded junction

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4837227B1 (en) * 1968-12-20 1973-11-09
JPS5683964A (en) * 1979-12-13 1981-07-08 Nec Corp Input protective device
KR900008746B1 (en) * 1986-11-19 1990-11-29 삼성전자 주식회사 Semiconductor device protecting a connection
DE3714647C2 (en) * 1987-05-02 1993-10-07 Telefunken Microelectron Integrated circuit arrangement
GB9215654D0 (en) * 1992-07-23 1992-09-09 Philips Electronics Uk Ltd A semiconductor component

Also Published As

Publication number Publication date
JPH07147384A (en) 1995-06-06
JP2611639B2 (en) 1997-05-21
US5521413A (en) 1996-05-28
KR0171646B1 (en) 1999-03-30

Similar Documents

Publication Publication Date Title
KR970072395A (en) Semiconductor devices
KR960032616A (en) Method of manufacturing self-aligned contact hole for semiconductor device
KR970067775A (en) Semiconductor devices
KR970067716A (en) Semiconductor device and manufacturing method thereof
KR850008052A (en) Semiconductor devices
KR880013239A (en) Connection hole formation method of semiconductor device
KR920015577A (en) Semiconductor device
KR970023863A (en) Semiconductor device and manufacturing method
KR900019155A (en) Contact Formation Method Using Etch Barrier
KR900019261A (en) Semiconductor device
KR900008668A (en) Semiconductor devices
TW200505055A (en) Light-emitting devices having an active region with electrical contacts coupled to opposing surfaces thereof and methods of forming the same
KR930009044A (en) Semiconductor devices
SE9900446D0 (en) Semiconductor device with deep substrate contacts
KR950015605A (en) Semiconductor device with contact portion having metal wiring
KR910008861A (en) Integrated circuit
KR890008949A (en) Semiconductor device and manufacturing method
KR970067916A (en) Low stress photodiode with low junction leakage
KR940008130A (en) Semiconductor device and manufacturing method thereof
KR960026934A (en) Bipolar transistor, semiconductor device comprising bipolar transistor and method of manufacturing same
KR970018597A (en) Semiconductor device and manufacturing method thereof
JPS6455873A (en) Semiconductor integrated circuit having surge protecting function
KR980005670A (en) Metal contact structure of semiconductor device
KR920015648A (en) Optical semiconductor devices
KR970063674A (en) Semiconductor devices

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20121002

Year of fee payment: 15

FPAY Annual fee payment

Payment date: 20131001

Year of fee payment: 16

FPAY Annual fee payment

Payment date: 20141007

Year of fee payment: 17

EXPY Expiration of term