KR950014683B1 - Semiconductor device and the manufacturing method - Google Patents

Abstract

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Description

Semiconductor device and manufacturing method thereof

1A to 1F are schematic cross-sectional views showing a process of forming an isolation region according to an embodiment of the present invention.

FIG. 2A is a schematic top view showing a memory cell array including isolation regions in accordance with the present invention. FIG.

2b is an enlarged cross-sectional view taken along the line 2B-2B in FIG. 2a.

3A to 3F are schematic cross-sectional views showing a process of forming a field oxide film according to the prior art.

4A is a schematic top view showing a memory cell array including a field oxide film according to the prior art.

4B is an enlarged cross-sectional view taken along the line 4B-4B in FIG. 4A.

* Explanation of symbols for main parts of the drawings

1 semiconductor substrate 2 first insulator layer

2a: insulator film 3: photoresist layer

3a: resist pattern 4: light

5: ion irradiation 6: channel stopper

7: Intrusion prevention layer 8: Second insulator layer

8a: sidewall insulator hemp 9: source / drain region

9a: ion irradiation

Moreover, in angle, the same code | symbol shows the same content or an equivalent part.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to an improvement in isolation regions between semiconductor circuit elements and methods of forming the same.

3A to 3F are cross-sectional views illustrating a process of forming a separation region using conventional selective oxidation.

Referring to FIG. 3A, an SiO ₂ film 22 having a thickness of about 500 GPa is formed on the Si substrate 21 by thermal oxidation.

The SiO ₂ film 22 is covered by a Si ₃ N film 23 deposited to a thickness of about 3000 Pa by CVD (chemical vapor deposition).

Referring to FIG. 3B, a resist layer is formed on the Si ₃ N ₄ film 24, and the resist pattern 24 is formed by patterning the resist layer.

Thereafter, an impurity region 26 is formed in the surface layer of the Si substrate 21 by ion irradiation as indicated by arrow 25 using the Si ₃ N ₄ film pattern 23a and the resist pattern 24 as a mask.

At this time, when the substrate 21 is P-conductive, boron ions are usually implanted at a dose ratio of 1 × 10 ¹³ cm ⁻² at an acceleration voltage of 20 to 30 kev.

Referring to FIG. 3D, the resist pattern 24 is removed.

Referring to FIG. 3E, the Si substrate 21 is thermally selectively oxidized using the Si ₃ N ₄ film pattern 23a as a mask to form a field oxide film 22a having a thickness of about 5000 kPa.

At this time, oxygen is also supplied in the transverse direction by diffusion at the end of the open hole of the Si ₃ N ₄ film 23a, thereby forming a bud beak 22b extending in the transverse direction by about 0.3 to 0.5 mu m in the field oxide film 22a.

Further, as indicated by the arrow 27 during the selective oxidation, the impurity region 4 (26) expands not only in the depth direction but also in the transverse direction by diffusion, and the bud beak 22b extends laterally by about 0.2 占 퐉 over the edge. To the channel stopper 26a.

It is preferable that the field oxide film 22a be as thick as possible in order to prevent the parasitic MOS (metal, oxide, semiconductor) transistor from being activated when a conductor line (not shown) is formed on the field oxide film 22a. Do.

However, when the field oxide film 22a becomes thick, the width of the bud beak 22b also becomes wider.

Therefore, when the power supply voltage of the semiconductor IC is 5V, the field oxide film 22a is usually formed to a thickness of about 5000 kV so that the threshold voltage of the parasitic MOS transistor is 10V or more and the bud beak 22b is not too wide.

Referring to FIG. 3F, the Si ₃ N ₄ film pattern 23a is removed.

Thereafter, for example, to form the source / drain regions 29 of the FETs (field effect transistors), ion implantation is performed as indicated by arrows 28 using the field oxide films 22a and 22b as masks.

At this time, since the channel stopper 26a extends laterally beyond the edge of the bird beak 22b, the channel stopper 26a penetrates into the source / drain region 29.

In order to prevent the MOS transistor from being activated, it is preferable that the impurity concentration of the channel stopper 26a be high.

However, if the impurity node of the channel stopper 26a becomes too high, the junction breakdown voltage of the source / drain region in contact with the channel stopper 26a is lowered.

Thus, as described in connection with FIG. 3C, boron ions 25 are implanted at a dose ratio of about 1 × 10 ¹³ cm ⁻² .

An example of a memory array including a field oxide film formed using selective oxidation with reference to FIG. 4A is shown in the top view.

In the upper half of FIG. 4A, the bit line BL is omitted for clarity of the drawing.

In the elongated semiconductor circuit element region 30, three source / drain regions (not shown) are formed side by side in the longitudinal direction thereof.

These three source / drain regions constitute a pair of FETs, and the center source / drain regions are shared by these two FETs, and are connected to the bit lines BL through the contact holes 31.

Each FET is turned on or off by the corresponding word line WL.

In the semiconductor element region 30 surrounded by the field oxide film 22a, a bird beak 22b having a width of about 0.3 탆 is widened around the semiconductor element region 30, and the effective width of the semiconductor small region 30 is narrowed.

With reference to FIG. 4B, the cross section along line 4B-4B in FIG. 4A is expanded and displayed.

A field oxide film 22a is formed on the Si substrate 21, and a bud beak 22b having a width of about 0.3 mu m is spread in the semiconductor element region 30. As shown in FIG.

Further, the channel stopper 26a, which is in contact with the bottom surfaces of SiO ₂ (22a, 22b) and is formed in the Si substrate, extends in the semiconductor element region 30 by a width of about 0.2 탆 beyond the edge of the bud beak 22b.

The gate oxide film 32 is formed on the surface of the Si substrate 21 between the edges of the opposite birdbeek 22b, and the word line WL is formed on the gate oxide film 32.

As is apparent from FIGS. 4A and 4B, when the width of the semiconductor device region 30 is 1 μm or more, the semiconductor device region 30 is not completely covered by the bird beak 22b. The channel stopper 26a does not spread throughout the inside, that is, when the width of the semiconductor element region 30 is 1 μm or more, the bird beak 22b or the channel stopper 26a spread inward from the periphery of the semiconductor element region 30. The area for forming the FET still further inside the) remains.

However, when the width of the semiconductor device region 30 is close to 1 µm, the effective area for forming the FET is narrowed, resulting in a decrease in the current value of the FET or an increase in the contact resistance in the contact hole 31. This deteriorates.

In particular, in a fine FET having a channel width of 1 μm or less, a so-called short channel effect such as a threshold voltage fluctuates due to the intrusion of the channel stopper 26a in the source / drain region.

In the case where the width of the semiconductor element region 30 is 1 占 퐉 or less, the channel stopper 26a spreads over the entire region of the semiconductor element region 30, making it difficult to form the FET. Further, when the width of the semiconductor device region 30 is 0.6 占 퐉 or less, the entire semiconductor device region 30 is covered by the bird beak 22b, making it impossible to form the FET.

It is therefore an object of the present invention to provide an isolation region and a method for forming the same that can improve the degree of integration without degrading the performance of a semiconductor IC.

A semiconductor device according to one aspect of the present invention is a semiconductor substrate having a main surface and a semiconductor circuit element formed on the main surface thereof and separated from each other by a separator insulator film and a separator insulator film having substantially sidewalls of a period. The first impurity region formed in the first impurity region and the element region formed by ion implantation in the plurality of semiconductor element regions and the substrate to the predetermined depth at the interface between the insulator film and the substrate is formed by ion implantation above a predetermined depth from the main surface. A sidewall insulator film formed by anisotropic etching is provided on a vertical sidewall of the second impurity region and the isolation insulator film formed simultaneously with the one impurity region.

In still another aspect of the present invention, a method of manufacturing a semiconductor device includes patterning a first insulator film so as to form a first insulator film on a main surface of a semiconductor substrate and forming an insulator film having a substantially vertical sidewall, and in the substrate, the insulator. To form a first impurity region up to a predetermined depth at the interface between the film and the substrate and to be separated from each other by the isolation insulator film, a predetermined depth at the main surface in the plurality of semiconductor element regions in which the semiconductor circuit elements should be formed. Anisotropically etch the second insulator film to ion implant to form a second impurity region at a position, to form a second insulator film covering the isolation insulator and the first main surface, and to leave the sidewall insulator film on a vertical sidewall of the isolation insulator film It is characterized by.

According to the present invention, since the isolation insulator film having substantially vertical sidewalls is formed using photolithography, the semiconductor device region can be defined with good accuracy.

Further, since the first impurity region serving as a channel stopper is formed by ion implantation through the isolation insulator film, a second impurity region serving as a so-called plate-through prevention layer can be formed at the same time.

Further, the sidewall insulator film can be formed in a width of about 0.1 mu m or less by anisotropic etching, so that the width of the semiconductor element region can be reduced.

For example, an impurity layer such as a source / drain of a FET is formed by ion implantation of not only the insulator film but also the sidewall insulator film as a mask, so that a portion where the source / drain region and the channel stopper overlap does not occur.

Therefore, the channel stopper does not deteriorate the characteristics of the FET.

EXAMPLE

1A to 1F are cross-sectional views illustrating a process of forming an isolation region according to the first embodiment of the present invention.

No. 1a also with reference to, for example a semiconductor of the P ^_ conductivity type (for example, silicon) a first insulator having a thickness of about 4000Å on the substrate 1 (for example SiO ₂₎ film 2 is deposited by CVD It is done.

The photoresist layer 3 is coated on the first insulator film 2.

The photoresist layer 3 is exposed by light 4 that has passed through a photomask (not shown).

Referring to FIG. 1B, the photoresist layer 3 is developed to form a resist pattern 3a.

By using the resist pattern 3a as a mask, the first insulator film 2 is anisotropically etched to form a separate insulator film 2a having a substantially vertical sidewall.

Referring to FIG. 1c, for example, boron ions 5 are implanted at a dose ratio of 1 × 10 ¹³ cm ⁻² at an acceleration energy of 160 KeV.

As a result, a first impurity region 6 having a thickness of about 2000 microseconds, which serves as a channel stopper, is formed under the insulator film 2a, and is in the semiconductor element region separated from each other by the insulator film 2a. A second impurity region 7 having a thickness of about 2000 microns is formed at a position of about 4000 microns deep on the surface of.

This second impurity region 7 serves to prevent plate-through of the FET formed later in the semiconductor element region.

Referring to FIG. 1D, the second insulator (eg, SiO ₂ ) film 8 is covered with a thickness within a range of 1000 to 2000 μs by CVD to cover the surface of the isolation insulator film pattern 2a and the semiconductor substrate 1. To be deposited.

The second insulator film 8 may be formed of a material different from that of the insulator film 2a.

Referring to FIG. 1E, the second insulator film 8 is anisotropically etched upward without using a mask.

As a result, the sidewall insulator film 8a is left on the vertical sidewall of the isolation insulator film 2a.

The width of the sidewall insulator film 8a varies depending on the thickness of the second insulator film 8 and a sidewall insulator film 8a having a small width of about 0.1 μm may be formed.

That is, the sidewall insulator film 8a can be formed to a good extent with a width considerably smaller than the conventional bird beak width.

Referring to FIG. 1f, for example, in order to form the source / drain region 9 of the FET, the isolation insulator film 2a uses the sidewall insulator film 8a as a mask, for example, the arsenic ion 9a has an energy of 50 KeV. At a dose ratio of 5 × 10 ¹⁵ cm ⁻² .

At this time, the channel stopper region 6 is separated from the channel stopper region 6 by a distance of about 0.16 占 퐉 corresponding to the width of the sidewall insulator film 8a of the source / drain region 9.

That is, the FET is not adversely affected by the channel stopper region 6 penetrating into the source / drain region 9.

Further, the thickness of the source / drain region 9 can be controlled by the acceleration energy of ions, and is usually formed to a thickness within the range of 1000 to 3000 kV.

Referring to FIG. 2A, an example of a memory cell array including an isolation region according to the present invention is shown in the top view.

In the upper half of this FIG. 2A, the bit line BL is omitted for clarity.

In the elongated semiconductor element region 10, three source / drain regions (not shown) are formed side by side in the longitudinal direction thereof.

These three source / drain regions form a pair of FETs, and the center source / drain regions are shared by these two FETs, and are connected to the bit lines BL through the contact holes 11.

Each FET is turned on or off by the corresponding word line WL.

A sidewall insulating film 8a having a width of about 0.1 탆 is formed along the inner circumference of the semiconductor small region 10 surrounded by the insulating insulator film 2a.

The bud beak 22b according to the prior art has a wide width of about 0.3 to 0.5 mu m, and precise control of the width is difficult.

On the other hand, the width of the sidewall insulator film 8 can be controlled more precisely, and the sidewall insulator film 8a having a width of only 0.1 m can be formed.

Therefore, the effective width of the semiconductor device region 10 is only slightly reduced by the sidewall insulator film 8a.

With reference to FIG. 2B, the cross section along the line 2B-2B in FIG. 2A is enlarged and displayed.

A separator insulator film 2a is formed on the semiconductor substrate 1, and a channel stopper 6 is formed directly under the separator insulator film 2a.

An impurity region 7 for preventing plate through is formed in the semiconductor element region 10 defined by a vertical sidewall of the isolation insulator film 2a that is accurately patterned by photolithography using anisotropic etching.

A sidewall insulator film 8a of about 0.1 mu m is formed on the vertical sidewall of the isolation insulator film 2a.

The gate insulator film 12 is formed on the surface of the semiconductor substrate 1 between the sidewall insulator films 8a facing each other, and the word line WL is formed on the gate insulator film 12.

As described above, according to the present invention, since the insulator film having the substantially vertical sidewall is formed using photolithography, the semiconductor device region can be defined to a good extent.

In addition, since the first impurity region serving as a channel stopper is formed by ion implantation passing through the isolation insulator film, the second impurity region serving as a so-called plate prevention layer can be formed at the same time.

Further, the sidewall insulator film can be formed to a width of about 0.1 탆 or less by anisotropic etching, so that the width of the semiconductor device region can be reduced.

For example, an impurity layer such as a source / drain of a FET is formed by ion implantation not only as the isolation insulator film but also as the sidewall insulator film as a mask, so that a portion where the source / drain region and the channel stopper overlap does not occur.

Therefore, the channel stopper does not deteriorate the characteristics of the FET.

Claims (2)

The semiconductor substrate 1 having a main surface, the isolation insulator film 2a formed on the main surface and having a substantially vertical sidewall, and the isolation insulator film 2a are separated from each other to form a semiconductor circuit element. A plurality of semiconductor element regions to be formed, a first impurity region formed by ion implantation in said substrate 1 by an ion implantation at an interface between said isolation insulator film 2a and said substrate, and in said element region; A second impurity region formed simultaneously with the first impurity region by the ion implantation at a position of a predetermined depth on a main surface, and a sidewall insulator film formed using anisotropic etching on a vertical sidewall of the isolation insulator film 2a ( 8a). A semiconductor device characterized by the above-mentioned. The first insulator film 2 is patterned to form a first insulator film 2 on the main surface of the semiconductor substrate 1 and to form an insulator film 2a having a substantially vertical sidewall. 1) a first impurity region up to a predetermined depth is formed at an interface between the isolation insulator film 2a and the substrate 1, and at the same time, a semiconductor circuit element is to be separated from each other by the isolation insulator film. In a plurality of semiconductor element regions, ion implantation is performed to form a second impurity region at a predetermined depth on the main surface, and a second insulator film 8 is formed to cover the separation insulator film 2a and the main surface. And anisotropically etching the second insulator film so as to leave the sidewall insulator film (8a) on a vertical sidewall of the isolation insulator film (8).