KR950013158B1 - Telecommunication/switching system - Google Patents

Abstract

a multiline interfacing unit for interfacing with a plurality of data transmitting lines; a plurality of reference communication clock generators independently operated from each other, for generating a reference communication clock; a clock module connected commonly with the plurality of reference communication clock generators, for generating various application communication clocks used during the communication by inputting any reference communication clock at an arbitrary time point and having a state port for indicating its own operation state; a communication processor connected to the state port of the clock module, for checking the state of the clock module in a polling manner during a predetermined period, changing the reference communication clock if the state is abnormal, and performing all kinds of controls during the communication; and a switching module connected to the multiline interfacing unit at the one side thereof and connected commonly to the communication processor and the clock module at the other side thereof to perform a softwarily switching operation according to channel.

Description

Telecom / Exchange Processing System

1 is a diagram showing the configuration of a general network to which both the prior art and the present invention can be applied.

2 is a diagram showing the node configuration of the network shown in FIG.

3 is a block diagram showing the configuration of the subscriber processor of FIG.

4A and 4B are block diagrams showing the structure of a conventional communication and exchange processing unit.

5A to 7 are block diagrams of a communication / switch processing system capable of preventing system downtime due to clock failure in accordance with the present invention.

8 through 10 are flowcharts illustrating a clock control method of a communication / switch processing system capable of preventing a system from crashing due to a clock failure according to the present invention.

* Explanation of symbols for main parts of the drawings

MLI: Multiline interface means CKM: Clock module

CPM: Communication Processor SWM: Switching Module

MEM: Memory RCV: Recovery Communication Clock Generator

LOC: Local Communication Clock Generator STD: Standard Communication Clock Generator

SP1: First status port SP2: Second status port

The present invention relates to a communication / switch processing system, and more particularly, to a system and a method for preventing a system from crashing due to a failure of a communication clock used to perform data transmission and reception.

In general, the clock can be classified into a process clock used to perform work at one node and a communication clock used to transmit and receive data with another node. The processor clock is a clock used by CPUs included in each node (NODE) and is generated and used through a crystal oscillator. However, the communication clock is related to data transmission and reception, and the pulse width must be closely managed compared to the process clock. There are various apparatuses for generating such a reference communication clock. The representative communication clock generator includes various stabilization circuits to stabilize the pulse width of the clock output from the oscillation circuit in addition to the oscillation circuit. The device itself consists of a high precision control system. Therefore, the standard communication clock generator (STD) has a huge difference in price compared with a general crystal oscillator. For this reason, each node (NODE) constituting a network system does not have one standard communication clock generator (STD), but each one constitutes a group (GROUP) so that one standard communication clock generator is used for each group. It is common to have

FIG. 1 shows the configuration of such a network, and each group includes several nodes (NODEs). In FIG. 1, when N1 among the nodes NODE included in Group-1 includes the standard communication clock generator STD, other nodes NODE included in the same group, that is, N2, N3, N4, N5, N6 , N7,… They receive the standard communication clock from the N1 to generate a communication clock using a clock recovery circuit (clock recovery cicuit). Here, each node NODE has the same configuration as that of the second degree. Referring to FIG. 2, the node NODE includes a communication and exchange processing unit 201 and a subscriber processing unit 202, and the communication and exchange processing unit 201 transmits data to other nodes included in the network. Or a part of performing exchange control of data transmitted / received through its own node at the same time as performing a required operation when receiving data from other nodes (NODEs), and the subscriber processor 202 is a node (NODE). A work area of subscribers belonging to the service provider has a configuration as shown in FIG. In FIG. 3, the subscriber controller 301 is a part for performing general control of the subscriber processor 202, and has an analog line interface (ALI) and an analog line interface for performing an interface to an analog terminal device. It includes a digital line interface (DLI) for performing an interface to the terminal device. An analog telephone 302 may be connected to the ALI, and the digital telephone 303, the facsimile 304, the monitor 305, the printer 306, the copier 307,... And the like can be connected.

On the other hand, the conventional communication and exchange processing unit 201 is configured as shown in Figs. 4a and 4b, the multi-line interface means (MLI), switching module (SWM), communication processor (CPM) and standard communication clock generator ( Or a multi-line interface means (MLI), a switching module (SWM), a communication processor (CPM), a recovery communication clock generator (RCV), and a memory (MEM). ) And a clock module (CKM). That is, as a device for generating a reference communication clock, FIG. 4a uses a standard communication clock generator STD and FIG. 4b uses a recovery communication clock generator RCV.

The reference communication clocks generated through such devices are applied to the clock module CKM to generate various application communication clocks used for communication. The switching module (SWM) is a part that performs a switching operation in software, one side is connected to the multi-line interface means (MLI) and subscriber processing unit, and the other side is connected to the communication processor (CPM) and clock module (CKM) It is connected to perform the switching operation according to the channel. There are 12 logic channels per line, the first channel being the channel through which the communication clock is transmitted and received, the second channel to the tenth channel is the channel for data transmission and reception between the communication processors of each node, If the 12 channel is a channel for data transmission and reception between the communication processor (CPM) and the subscriber processing unit, and the switching module (SWM) is the first channel, the multi-line interface means (MLI) is connected to the clock module (CKM) In the case of the second to tenth channels, the multi-line interface means (MLI) is connected to the communication processor (CPM). In case of the eleventh and twelfth channels, the communication processor (CPM) is connected to the subscriber processing unit (CPM). 202).

However, the communication and exchange processing unit 201 having the above configuration does not have a countermeasure against a clock failure, so that the down phenomenon of the communication and exchange processing unit 201 appears. In other words, communication with other nodes becomes impossible. Also, as can be seen in FIG. 1, even if its communication and exchange processing unit 201 is not down, communication is not possible if all communication and exchange processing units 201 of the adjacent nodes NODE are down. Therefore, it is necessary to prevent the down phenomenon of the communication and exchange processing unit 201 as much as possible.

The present invention is to solve the problems of the prior art, and to provide a clock control method of the system of the communication / exchange processing system for preventing the down phenomenon of the communication and exchange processing unit that may occur due to communication clock failure.

Another object of the present invention is to provide a communication / switching processing system capable of performing the above method.

In order to achieve the above object, a clock control method of a communication / exchange processing system of the present invention generates a variety of application communication clocks by selectively inputting a plurality of reference communication clock generators and a plurality of reference communication clocks, and has a status port. Software according to a channel and a communication processor for controlling communication / switching processing, a plurality of clock modules for which any one is active at any time, a connection process for connecting to each node on a network, and a control for communication / switching processing. A method for preventing downtime of a system due to a communication clock failure in a communication / switch processing system having a switching module for performing a switching operation, wherein the status port of the clock module is polled at a predetermined interval to determine whether there is a clock failure. Judging; Determining whether there is a changeable reference communication clock in a clock module that is in an active state when a clock failure occurs; Changing a reference communication clock to be input when there is a changeable reference communication clock in the clock module in an active state; Determining whether there is a clock module in the stand-by state when there is no changeable reference communication clock in the clock module in the active state; If there is no clock module in the stand-by state, bringing the system down; otherwise, switching the stand-by clock module to the active state and repeating the above steps. It is characterized by.

In order to achieve the above object, the present invention provides a communication / exchange processing system comprising: multi-line interface means for performing an interface with a plurality of data transmission lines; A plurality of reference communication clock generators operating independently of each other and generating a reference communication clock as a reference for communication, and the plurality of reference communication clock generators, are commonly connected to input any one reference communication clock at any time. A plurality of clock modules for generating various application communication clocks used for communication and having a status port for indicating an operation state thereof; A state of a clock module that is connected to the status ports of the plurality of clock modules and selectively activates one of the plurality of clock modules at any given time and is in an active state in a polling manner for a predetermined period of time. A communication processor for changing various reference communication clocks inputted by the clock module in the active state or changing the active clock module in case of abnormality, and performing various types of communication control; And a switching module connected to the multi-line interface means on one side and commonly connected to the communication processor and the plurality of clock modules to perform a software switching operation according to a channel.

Next, the present invention will be described in more detail with reference to the accompanying drawings.

First, the duplication of the clock module CKM of the communication and exchange processing unit 201 will be described with reference to FIGS. 5A to 5B. 5A shows a communication and exchange processing unit 201 using a standard communication clock generator STD as a reference communication clock generator, and FIG. 5B shows a communication and exchange processing unit using a recovery communication clock generator RCV as a reference communication clock generator ( 201). 5A and 5B, the first clock module CKM1 and the second clock module CKM2 are means for inputting a reference communication clock to generate various application communication clocks, respectively, and only one at any one time point. This is selectively activated. In addition, the first clock module CKM1 includes a first status port SP1 and the second clock module CKM2 includes a second status port SP2. The output terminals of the first state port and the second state port are connected to the communication processor (CPM) so that the communication processor (CPM) reads the values every predetermined period to determine the state. FIG. 8 is a flowchart illustrating a clock control method performed by the communication processor CPM when the clock module CKM is duplicated.

In FIG. 8, step 801 is a step of reading the status port of the clock module CKM, wherein the status port value of the clock module in the active state among the first clock module CKM1 and the first clock module CKM2 is shown. You will read The value output by the status port can vary depending on its configuration. An example is shown in Table 1 below.

Table-1

According to Table-1, when the value of D1 is "1", it means that the corresponding clock module (CKM) is in stand-by. If "0", it is currently in the active state or a failure occurs and is waiting. It is not stand-by. In addition, when the value of D0 is "1", it indicates that the reference communication clock, such as the standard communication clock or the recovery communication clock, is being serviced. Otherwise, it indicates that the reference communication clock is not being serviced. In step 802, it is determined whether a value of a predetermined bit of the status port has a value. In the example shown in Table-1, the process proceeds to step 803 or step 804 according to the value of D0. Step 803 is a step of determining whether or not the service clock is synchronized with the communication counterpart substantially when there is a service clock. The frame synchronization signal is detected in data input through the multi-line interface means MLI. It is determined whether or not. That is, if the synchronization is performed correctly, the frame synchronization signal is detected. Otherwise, the frame synchronization signal is not detected. If the frame synchronization signal is detected, the frame synchronization signal is detected. In step 801, the values of the status port of the clock module CKM are checked in a polling manner every predetermined period.

Step 804 is performed when there is no reference communication clock serviced to the clock module CKM in the active state, and performs a predetermined warning. The warning may be performed by generating a buzzer sounding a warning or displaying a warning message on a predetermined liquid crystal panel. Operation 805 is performed when a frame synchronization signal is not detected, and performs a warning. In this case, the warnings performed in steps 804 and 805 may appear in different forms so that the user may know what kind of failure has occurred. Step 806 is a step of determining whether there is a clock module CKM which is in a stand-by state, and is performed by checking a value of a predetermined bit in the status port of each clock module CKM. At this time, if there is no clock module (CKM) in the stand-by state, the communication and exchange processing unit should be turned down after the warning is performed, and there is a clock module in the stand-by state. In this case, after the clock module CKM is replaced, the process proceeds to step 801 to check the status port once again. If there are two or more clock modules CKM in stand-by, the priority is set for each clock module CKM so that the clock module CKM having a high value is selected first. .

6 is a dual reference communication clock generator in order to prevent down due to clock failure of the communication and exchange processing unit. The reference communication clock generator includes a standard communication clock generator (STD), a recovery communication clock generator (RCV), and a local. There may be a communication clock generator (LOC). Here, the local communication clock generator (LOC) is a relatively low price reference communication clock generator, such as a clock generator used in the subscriber processor 202, to give the lowest priority to prepare for the worst condition. In this case, an example of the output value indicated by the status port of the clock module CKM is shown in Table 2 below.

TABLE 2

When the value of each bit in Table-2 is "0", it indicates that each communication clock is not serviced, and when it is "1", it indicates that each communication clock is serviced.

As described above, a method of controlling the clock in the communication and exchange processing unit in which the clock module CKM and the reference communication clock generator are duplicated will be described with reference to FIG.

9, step 901 is a step of reading a status port of a clock module CKM in an active state, and step 902 is a step of checking whether there is a service clock. If there is a clock that is being serviced, it is determined whether a frame synchronization signal is detected in step 906 to determine whether the clock is synchronized. If the clock is operated in synchronization at step 906, the process proceeds to step 907 to perform a communication service for a predetermined period. Steps 908 to 910 describe the communication service for a predetermined period in more detail as described above. The clock module at the step of checking the status port of the clock module CKM is finished in order to control the polling time. The polling time of (CKM) is set to a predetermined value. At this time, the polling time of the clock module CKM is designed to decrease gradually as time passes, so that when the value is 0, the communication processor CPM reads the status port of the clock module CKM again. . Step 911 is a step of checking whether there is a replaceable clock when the frame synchronizing signal is not detected. When there is a replaceable clock, the reference communication clock input to the clock module CKM is changed. Step 903 is a step of generating a message that warns that a failure has occurred in the clock module CKM, and step 904 is checking whether there is a clock module CKM to replace. If there is no clock module (CKM) in the standby state, a warning message is generated and the communication and exchange processing unit is down. If there is a clock module (CKM) in the standby state, the active clock module (CKM) is changed. In step 901, the status port is checked again. Here, when the clock module CKM fails and another clock module CKM is selected, the bit of the status port indicating the standby state of the clock module CKM indicates "not in standby"-for example, "0". . At this time, if the fault of the clock module CKM is overcome through repair or the like, the bit value of the status port indicating the standby state is set back to "standby state", for example, "1".

7 is a block diagram showing the duplication of the clock module (CKM), the reference communication clock generator and the switching module (SWM) to prevent the down phenomenon of the communication and exchange processing unit caused by the clock failure, multi-line interface means (MLI) And the first switching module SWM1, the second switching module SWM2, the first clock module CKM1, the second clock module CKM2, and the plurality of reference communication clock generators RCV, LOC, STD, ... And a communication processor (CPM) and a memory (MEM).

In FIG. 7, the first switching module SWMl and the second switching module SWM2 include the multi-line interface means MLI, the first clock module CKM1, the second clock module CKM2, and a communication processor. CPM), each of which is selectively activated at any one point in time. The clock control method of the communication and exchange processing unit configured as described above will be described with reference to FIG.

In FIG. 10, after reading the status port of the clock module CKM in the active state in step 1001, it is determined whether or not the clock serviced in step 1002 exists. If there is a clock that is being serviced, it is determined in step 1003 whether the frame synchronization signal is detected to determine whether the clock is synchronized correctly or not. When the clock is synchronized with the clock of the other node with which the communication clock is in sync, and the frame synchronization signal is detected, the process proceeds to step 1001 to check the state again after performing the communication service for a predetermined period in step 1004. If the frame synchronization signal is not detected in step 1003, the clock being serviced is not synchronized with the other party with whom the communication is being performed.

Therefore, if no frame synchronizing signal is detected, it is checked whether there is a clock to replace. If there is a clock to be replaced, after the clock is replaced, the process proceeds to step 1003 to check whether the frame sync signal is detected again. If there is no clock to replace, a warning is performed in step 1007 and the process proceeds to step 1008. On the other hand, if there is no clock serviced by the clock module CKM in the active state in step 1002, the operation proceeds to step 1008 after the warning is performed in step 1007. In step 1008, it is determined whether there is a clock module CKM to be replaced. If there is a clock module CKM to be replaced, the controller 100 replaces the clock module CKM in step 1009 and then proceeds to step 1001 to check the status again. If there is no clock module CKM to replace in step 1008, after the warning is performed in step 1010, the process proceeds to step 1011 to check whether there is a switching module SWM to replace. If there is a switching module SWM to be replaced in step 1011, the process proceeds to step 1001 in order to check the state again after changing the switching module SWM that is activated in step 1012. On the other hand, if there is no switching module (SWM) to replace in step 1011, after the warning is performed, the communication and exchange processing unit is down.

Table 3 shows an example of values indicated by output bits of the status port of each clock module CKM when the duplication of the reference communication clock generator and the clock module CKM are simultaneously performed.

Table-3

In Table-3, when the bit D3 is "1", it indicates that it is in a standby state, and when it is "0", it indicates that it is not waiting or is active due to a failure, and bits D2, D1, and D0 are each "." When it is 1 ", the reference communication clock is serviced. When it is" 0 ", it indicates that the reference communication clock is not serviced.

As described above, the present invention is to reduce the phenomenon that the system is down due to the failure of the communication clock in the communication and exchange processing unit as much as possible, has the effect of improving the reliability of the communication network.

Claims (12)

A communication / switching processing system constituting one network, comprising: multi-line interface means for performing an interface with a plurality of data transmission lines; A plurality of reference communication clock generators operating independently of each other and generating a reference communication clock; It is connected in common with the plurality of reference communication clock generators and inputs any one reference communication clock at any time to generate various application communication clocks used for communication, and has a status port for indicating its own operation state. A clock module; Connected to the status port of the clock module and checking the state of the clock module in a polling manner for a predetermined period of time, in case of abnormality, changing a reference communication clock inputted by the clock module and performing various control on the communication. A communication processor; And a switching module connected to the multi-line interface means on one side and commonly connected to the communication processor and the clock module to perform a software switching operation according to a channel. . The standard of claim 1, wherein the plurality of reference communication clock generators are configured as an oscillating circuit having a high-performance stabilization circuit and used as a reference communication clock on its own communication node and simultaneously transmitted to other communication nodes on the network. A standard communication clock generator for generating a communication clock; A recovery communication clock generator configured to include a phase locked loop and receiving a standard communication clock from another communication node on the network through a predetermined channel and generating a clock synchronized with the standard communication clock; A communication / exchange processing system comprising a local communication clock generator for generating a reference communication clock used only in a communication node to which the network belongs. Multi-line interface means for performing an interface with a plurality of data transmission lines; A plurality of reference communication clock generators operating independently of each other and generating a reference communication clock; A plurality of communication ports connected in common with the plurality of reference communication clock generators to generate a variety of application communication clocks used for communication by inputting any one reference communication clock at an arbitrary time point and having a status port for indicating an operation state; Clock modules of; Connected to the status ports of the plurality of clock modules to selectively activate one of the plurality of clock modules at any one time and to poll the state of the clock module being active in a polling manner at predetermined time intervals. A communication processor for changing a reference communication clock inputted by a clock module in an active state or changing a clock module that is activated when there is an error and performing various kinds of control in communication; And a switching module connected to the multi-line interface means on one side and connected to the communication processor and the plurality of clock modules to perform a software switching operation according to a channel. . 4. The standard of claim 3, wherein the plurality of reference communication clock generators are composed of an oscillating circuit having a high density stabilization circuit and used as a reference communication clock in its own communication node and simultaneously transmitted to other communication nodes on the network. A standard communication clock generator for generating a communication clock; A recovery communication clock generator configured to include a phase locked loop and receiving a standard communication clock from another communication node on the network through a predetermined channel and generating a clock synchronized with the standard communication clock; A communication / exchange processing system comprising a local communication clock generator for generating a reference communication clock used only in a communication node to which the network belongs. A plurality of reference communication clock generators, a clock module having a status port for selectively inputting one of the plurality of reference communication clocks to generate various application communication clocks, and a communication processor for performing communication / exchange control operations And a method for preventing downtime of a system due to a communication clock failure in an exchange processor, the method comprising: reading a status port of the clock module at a predetermined interval to determine whether there is a clock failure; And changing a reference communication clock input by the clock module when a clock failure occurs. 6. The method of claim 5, wherein the method performs a predetermined warning when a clock failure occurs. A plurality of reference communication clock generators, a plurality of clock modules that selectively input one of the plurality of reference communication clocks to generate various application communication clocks, have a status port, and any one is active at any time; Communication in a communication / exchange processing system comprising a multi-line interface means for performing connection processing with a data transmission line, a communication processor for performing control in communication / exchange processing, and a switching module for performing a software switching operation according to a channel. A method for preventing downtime of a system due to a clock failure, the method comprising: reading a status port of the active clock module at a predetermined interval to determine whether there is a clock failure; Determining whether there is a changeable reference communication clock in a clock module that is in an active state when a clock failure occurs; Changing a reference communication clock to be input when there is a changeable reference communication clock in an active clock module; Determining whether there is a clock module in the standby state when there is no changeable reference communication clock in the clock module in the active state; If there is no clock module in the standby state, bringing down the system; otherwise, converting the clock module in the standby state to an active state and repeatedly performing the above steps. Clock control method. 8. The method of claim 7, wherein the method performs a warning when there is a clock failure. The method of claim 7, wherein the determining of the presence or absence of a clock failure comprises determining that there is a clock failure when no frame synchronization signal is detected in the received data, and determining that there is no clock failure when the frame synchronization signal is detected. A clock control method of a communication / switch processing system. 8. The clock control method according to claim 7, wherein the method performs a warning when there is no reference communication clock waiting in the clock module in an active state. 8. The method of claim 7, wherein the method performs a warning if there is no waiting clock module when the clock module needs to be changed. A plurality of reference communication clock generators, a plurality of clock modules that selectively input one of the plurality of reference communication clocks to generate various application communication clocks, have a status port, and any one is active at any time; A multi-line interface means for performing connection processing with data transmission lines, a communication processor for performing control in communication / exchange processing, and a software switching operation performed according to a channel, and a plurality of only one active at any one point in time A method for preventing downtime of a system due to a communication clock failure in a data communication system having switching modules, the method comprising: reading a status port of the clock module at a predetermined interval to determine whether there is a clock failure; Determining whether there is a changeable reference communication clock in a clock module that is in an active state when a clock failure occurs; Changing a reference communication clock input when there is a changeable reference communication clock in the clock module in an active state; Determining whether there is a clock module in the standby state when there is no existing communication clock that can be changed in the clock module in the active state; Changing the active clock module when there is a clock module in the standby state and repeating the above steps; Determining whether there is a switching module in the standby state when there is no clock module in the standby state; If there is no switching module in the standby state, the system is down; otherwise, the switching module in the standby state is switched to the active state, and repeating the above steps. Clock control method.