KR950011727B1 - Semiconductor memory device - Google Patents

Abstract

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Description

Semiconductor memory

1 is a circuit diagram according to a first embodiment of the present invention.

2 is a timing diagram according to the embodiment of FIG.

3 is a main circuit diagram according to another embodiment of the present invention.

4 is a main circuit diagram according to another embodiment of the present invention.

5 is a circuit diagram of a conventional circuit.

* Explanation of symbols for main parts of the drawings

13: memory cell 15: fuse

17: Combined recording and reading transistor 19: Bit line

21: high voltage application pad 23: word line

25: hang decoder 27: diode

31 transistor 33 inverted boost circuit

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to an electrically programmable read / write memory.

[Traditional Technology and Problems]

Conventionally, some of the electrically programmable read-only memory cells have been proposed, such as a combination of a fuse and a transistor, or programming data by destroying a diode or an oxide film. Among them, memory cells in which fuses, write transistors, and read transistors are combined have characteristics such as easy manufacturing process, high reliability, and easy programming. Figure shows the circuit diagram.

However, in the conventional circuit of FIG. 5, since the memory transistor 1 is composed of three elements, the write transistor 3, the read transistor 5, and the fuse 7 of one memory cell 1, the area of the cell 1 is large. It becomes relatively large. For this reason, in the case of being used as a spare cell for defective relief, for example, there is a drawback that if the number of spare cells is increased to increase the defective relief effect, the chip size increases.

In addition, in order to solve the above drawback, it is considered to use a combination of write and read transistors. However, in this case, the bit line 9 and the high voltage applying pad 11 are directly connected to each other. (11) and a parasitic capacitance such as a prober for applying a voltage thereto are added to the bit line 9 as it is, so that high speed operation becomes very difficult.

[Purpose of invention]

SUMMARY OF THE INVENTION The present invention was devised in view of the above-described problems, and provides a semiconductor memory device in which a memory cell is constituted by one transistor and a fuse by combining the functions of writing and reading into one transistor so that the above problem does not occur. Has its purpose.

[Configuration of Invention]

The present invention for achieving the above object is an electrically programmable read-only semiconductor memory device comprising: a memory cell comprising a series connection of one write / read transistor and one fuse; A high voltage applying pad to which a high voltage for melting the fuse is applied when writing data on the data, and a line for being connected to a series connection of the memory cell and a high voltage applied to the high voltage applying pad to the series connection. And a bit line, which serves as a line for reading data from the memory cell, between the bit line and a high voltage gadpad, electrically connecting them to a data proxy, and electrically separating them when reading data. The connection separating means and one end is connected between the high voltage applying pad and the connection separating means By having a grounding transistor connected to a ground terminal is characterized in that configured.

[Action]

In the apparatus of the present invention configured as described above, the data write back is subjected to a snap back operation to the write / read transistor by applying a high voltage to the preliminary bit line through the connection separating means from the high-input pad. Then, the fuse is blown and the fuse is blown to program the data.

When the data is read out, the semiconductor device and the high voltage applying pad are analyzed by the connection separating means while the recording / reading transistor is turned on. In this way, the high voltage applying pad and the prober applying voltage to the high voltage applying pad are analyzed. Parasitic capacitances such as and the like are separated from the bit lines, thereby enabling data to be read at high speed.

EXAMPLE

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows one embodiment of the present invention, wherein each memory cell 13 is composed of one fuse 15 and one write / read transistor 17.

One end of the fuse 15 is connected to the corresponding semiconductor 19, and the other end is connected to the drain of the write / read transistor 17 (the drain of the write / read transistor 17 is a bit line 19). ), And the source may be connected to the fuse 15]. A high voltage application pad 21 is connected to each bit line 19 via a diode 27, and a gate of the write / read transistor 17 is connected to a corresponding word line 23. As shown in FIG. Each word line 23 is connected to the output of the row decoder 25, and each row decoder 25 receives an address signal and a write enable signal / WE.

FIG. 2 is a timing diagram of the recording and reading of the present embodiment shown in FIG. 1. In the recording cycle, the program signal / PGM is first set to the "L" level, and then the high voltage applying pad of one selected bit line is shown. A high voltage (about 10 V) is applied to the 21 as the external voltage V _EX . Next, the address is sequentially scanned, and if the fuse is blown, the write enable signal / WE is set to the "L" level. As a result, one memory cell is selected to write and write the cell. The read / write transistor 17 performs a snapback operation, and current flows from the high voltage application pad 21 to the diode 27, the bit line 19, the fuse 15, and the write / read transistor 17. (15) is melted.

On the other hand, in the read cycle, the external voltage V _EX is at the "L" level, the program signal / PGM is at the "H" level, and the grounding transistor 29 is conducted so that the diode 27 is in the reverse biased state. Parasitic capacitance such as an application pad 21 and a prober for applying a voltage thereto is separated from the bit line 19. Therefore, the capacity of the bit line 19 does not become large and high-speed operation is attained.

FIG. 3 shows a main circuit section according to another practical example of the present invention. The circuit of FIG. 3 uses a transistor 31 having a gate and a drain connected instead of the diode 27 of FIG. This transistor 31 can have the same function as the diode 27 of FIG. 1 by setting the channel width sufficiently large.

FIG. 4 connects the gate of the transistor 31 in FIG. 3 with the output of the inverting booster circuit 33, and applies a program signal (/ PGM) to the input of the inverting booster circuit 33, thereby recording. A modification is shown in which a sufficiently high voltage is applied to the gate of the transistor 31 to supply a sufficient current. When the readout is performed, the program voltage / PGM is set to the "H" level, and the output of the inverting booster circuit 33 is set to the ground level, whereby the transistor 31 is turned off. It can have the same function as.

On the other hand, the reference numerals written along the components of the claims of the present application to facilitate the understanding of the present invention, not intended to limit the technical scope of the present invention to the embodiments shown in the drawings.

[Effects of the Invention]

As described above, according to the present invention, one memory cell is composed of one read / write transistor and a fuse connected in series thereto, and the bit line is electrically separated from the high voltage application pad when data is read from the cell. By doing so, it is possible to reduce the size of the memory cell without causing a decrease in data read speed.

Claims (4)

An electrically programmable read-only semiconductor memory device comprising: a memory cell (13) including a series connection of one write / read transistor (17) and one fuse (15), and the memory cell (13) ) Is connected to a high voltage applying pad 21 to which a high voltage for melting the fuse 15 is applied, and a serial connector of the memory cell 13, and the high voltage applying pad 21 ) Between the bit line 19 and the semiconductor 19 and the high voltage applying pad 21 which serve as a line for transferring a high voltage applied to the serial connection body and a line for reading data from the memory cell 13. A connection separating means for electrically connecting the two to the data storage, and one end being electrically separated between the two at the time of reading the data, and the other end being connected between the high voltage applying pad 21 and the connection separating means. A semiconductor memory device, characterized in that the stage comprises a grounding transistor (29) connected to a ground terminal. The semiconductor memory device according to claim 1, wherein said connection disconnecting means is a diode (27). 2. The semiconductor memory device according to claim 1, wherein said connection separating means is a switching element (31) which is controlled to an on state at the time of data writing and to an off state at the time of reading. The semiconductor memory device according to claim 1, wherein said grounding transistor (29) is a normal transistor and is controlled by a program signal (/ PGM) applied to a gate.