KR950011032B1 - Josephson junction field effect transistor and its making method - Google Patents
Josephson junction field effect transistor and its making method Download PDFInfo
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- 230000005669 field effect Effects 0.000 title claims description 16
- 238000000034 method Methods 0.000 title claims description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 125000006850 spacer group Chemical group 0.000 claims abstract description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 7
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims 5
- 229910052738 indium Inorganic materials 0.000 claims 1
- 229910052758 niobium Inorganic materials 0.000 claims 1
- 125000002524 organometallic group Chemical group 0.000 claims 1
- 229910052718 tin Inorganic materials 0.000 claims 1
- 239000002887 superconductor Substances 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 230000005668 Josephson effect Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000002679 ablation Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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Abstract
Description
제1도는 본 발명에 따른 조셉슨 접합 전계효과 트랜지스터의 구조를 나타낸 단면도.1 is a cross-sectional view showing the structure of a Josephson junction field effect transistor according to the present invention.
제2(a)도 내지 제2(c)도는 본 발명에 따른 조셉슨 접합 전계효과 트랜지스터의 제조공도.2 (a) to 2 (c) is a manufacturing process of the Josephson junction field effect transistor according to the present invention.
제3도는 본 발명의 조셉슨 접합 전계효과 트랜지스터의 전류-전압 특성을 나타낸 표.3 is a table showing current-voltage characteristics of a Josephson junction field effect transistor according to the present invention.
본 발명은 초전도체(superconductor) 전극(즉, 소오스와 드레인) 사이에 2차원 전자기체(two dimensional electron gas)를 이용한 조셉슨 접합 전계효과 트랜지스터(Josephson Junction field effect transistor) 및 제조방법에 관한 것이다.The present invention relates to a Josephson junction field effect transistor using a two-dimensional electron gas between a superconductor electrode (ie, source and drain) and a method of manufacturing the same.
초전도 성질을 이용한 조셉슨 소자는 일찍부터 고안, 발달되어 있다.Josephson devices using superconducting properties have been invented and developed early.
통상 조셉슨 소자란 두개의 초전도체가 얇은 절연막(부도체)으로 절연되어 있을때 쿠퍼쌍 관통(Cooper pair tunneling)에 의해 두 초전도체 사이에 전위차가 없어도 직류전류가 흐르고, 바이어스(bias)를 걸어주면 전압에 비례하는 주파수의 교류가 발생하는 조셉슨 효과를 응용한 소자를 말한다.In general, Josephson element means that when two superconductors are insulated with a thin insulating film (insulator), DC current flows even though there is no potential difference between two superconductors by Cooper pair tunneling, and when bias is applied, it is proportional to the voltage. Refers to a device to which the Josephson effect of alternating frequency is applied.
특히, 두개의 초전도체 사이의 접합 부분으로서 얇은 부도체대신 도체를 사용하는 경우에는 근접효과(proximity effect)에 의해 쿠퍼쌍 관통이 가능하여 조셉슨 효과가 나타난다.In particular, when a conductor instead of a thin nonconductor is used as a junction between two superconductors, the Josephson effect appears because the cooper pair can be penetrated by a proximity effect.
이와 같이 대부분의 조셉슨 소자는 접합부분에 절연체 또는 금속을 사용하는 초전도체-절연체-초전도체 또는, 초전도체-도체-초전도체의 샌드위치 형태(sandwitch type)의 구조로서, 다이오드 형태의 두단자소자이었다.As described above, most Josephson devices are diode-shaped two-terminal devices having a sandwich type structure of a superconductor-insulator-superconductor or a superconductor-conductor-superconductor using an insulator or metal at a junction.
이러한 조셉슨 접합소자는 기존의 반도체 소자에 비해 기능이 훨씬 우수한 것으로 알려져 있기는 하나(수 ps의 스위칭 시간, 수 μW의 소모전력), 보다 실용적인 세단자 소자, 즉 트랜지스터 형태의 소자개발은 아직 미진한 실정이다.Although the Josephson junction device is known to perform much better than the conventional semiconductor device (switch time of several ps, power consumption of several μW), development of a more practical three-terminal device, that is, a transistor type device, is still insufficient. to be.
그 이유로는 쿠퍼쌍(Cooper pair)이 관통 또는 침투할 수 있는 거리, 즉 접합부분의 길이가 절연체의 경우엔 수집 Å, 도체의 경우엔 2000~3000Å에 지나지 않아, 접합부분의 성질을 제조할 수 있는 게이트 전극 장착이 거의 불가능하기 때문이다.The reason for this is that the distance that the Cooper pair can penetrate or penetrate, that is, the length of the joint is only a collection 수집 for insulator and 2000 to 3,000 엔 for conductor, so that the properties of the joint can be manufactured. This is because mounting a gate electrode is almost impossible.
그러나, 다음에 상세히 설명될 GaAs/AlGaAs 이종 접합구조에 의해 생성된 2차원 전자기체를 조셉슨 접합부분으로 이용하면, 접합부분의 길이가 수십~수백 μm까지 확정될 수 있으므로 현재의 리소그라피 기술(lithography technique) 수준으로 충분히 게이트 장착이 가능하므로 트랜지스터의 응용이 가능하게 된다.However, using a two-dimensional electromagnetic body produced by a GaAs / AlGaAs heterojunction, which will be described in detail later, as the Josephson junction, the length of the junction can be determined from tens to hundreds of micrometers. It is possible to mount the gate sufficiently at the level of) to enable the application of the transistor.
본 발명에서는 전술한 바와 같이 조셉슨 접합부분으로서 고이동도(high mobility)와 조절 가능한 면전하밀도(controllable sheet carrier density)를 갖는 2차원 전자기체를 사용한다.In the present invention, as described above, the Josephson junction uses a two-dimensional electromagnetic body having high mobility and controllable sheet carrier density.
2차원 전자기체란 전자들이 수십 Å 정도의 얇은 층에 구속되어 있는 상태의 전자계(electron system)를 말하는 것으로, 근래에 이르러 분자선 에피택시(Molecular Beam Epitaxy) 방법 또는 유기 금속 화학기상증착(Metal Organic Chemical Vapor Deposition) 방법과 같은 고순도 반도체 박막 결정성장 기술의 발전에 힘입어 이와 같은 2차원 전자기체를 반도체 이종접합 구조에서 쉽게 형성할 수 있다.A two-dimensional electromagnetic body refers to an electron system in which electrons are confined to a thin layer of several tens of micrometers. In recent years, a molecular beam epitaxy method or a metal organic chemical vapor deposition method is used. Thanks to the development of high purity semiconductor thin film crystal growth techniques such as the Vapor Deposition method, such a two-dimensional electromagnetic body can be easily formed in a semiconductor heterojunction structure.
2차원 전자기체의 전자밀도는 금속에 비해 비교적 낮아 페르미 파장이 수백 Å정도, 자유비행 거리가 수십 μm 정도이다. 따라서 2차원 전자기체층을 제1도에 도시된 바와 같이 가로방향으로 두 초전도체 사이에 접합시키고, 그 접합부분의 길이(ℓ)를 2차원 전자 기체층 내의 전자 자유비행 거리와 비슷하거나 작게 만들고, 초전도체의 근접효과에 의해 유도된 쿠퍼쌍이 2차원 전자기체를 통하여 흐르게 되고 종래의 조셉슨 소자에서 나타나는 효과와 동일한 조셉슨 효과를 얻을 수 있게 된다.The electron density of two-dimensional electromagnetic bodies is relatively lower than that of metals, and the Fermi wavelength is several hundreds of kilohertz and the free flight distance is several tens of micrometers. Thus, the two-dimensional electromagnetic layer is bonded between the two superconductors in the horizontal direction as shown in FIG. 1, and the length (L) of the junction portion is similar to or smaller than the electron free flight distance in the two-dimensional electron gas layer, Cooper pairs induced by the proximity effect of the superconductor flow through the two-dimensional electromagnetic body, and the same Josephson effect as in the conventional Josephson device can be obtained.
이 경우 접합 부분의 길이가 최대 수십 μm 정도로 충분히 커지므로 접합 부분의 상부에 게이트를 형성하여 전계효과에 의해 2차원 전자 기체층의 전자 밀도를 제어할 수 있고, 그 결과 초전도 전류(supercurrent)를 제어할 수 있다.In this case, since the length of the junction portion is sufficiently large up to several tens of μm, a gate is formed on the junction portion to control the electron density of the two-dimensional electron gas layer by the electric field effect, thereby controlling the superconducting current. can do.
따라서, 본 발명은 2차원 전자기체를 이용한 조셉슨 접합 전계효과 트랜지스터 및 그 제조방법을 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide a Josephson junction field effect transistor using a two-dimensional electromagnetic body and a method of manufacturing the same.
이제부터 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2(a)도 내지 제2(c)도는 본 발명에 따른 조셉슨 접합 전계효과 트랜지스터의 제조공정도이다.2 (a) to 2 (c) are manufacturing process diagrams of the Josephson junction field effect transistor according to the present invention.
제2(a)도를 참조하면, 반절연성 GaAs의 반도체기판(11)의 상부에 분자선 에피택시(Molecular Beam Epitaxy) 또는 유기 금속 화합증기증착(Metal Organic Chemical Vapor Deposition) 방법으로 버퍼층(13), 스페이서(spacer:15), 캐리어 소오스층(carrier source layer:17), 캡층(cap layer:19)을 순차적으로 형성한다.Referring to FIG. 2 (a), the buffer layer 13 may be formed on the semiconductor substrate 11 of semi-insulating GaAs by a molecular beam epitaxy or a metal organic chemical vapor deposition method. A spacer 15, a carrier source layer 17, and a cap layer 19 are sequentially formed.
상기에서 버퍼층(13)은 반도체기판(11)의 결정 결함등이 확산되는 것을 방지하는 것으로 불순물이 도핑되지 않은 GaAs로 형성된다. 스페이서(15)는 불순물이 도핑되지 않은 상기 버퍼층(13)을 이루는 GaAs 보다 에너지 밴드 갭이 큰 AlGaAs로 형성되어 상기 버퍼층(13)에 전자 및 초전도전류의 이동 통로가 되는 2차원 전자 기체(21)가 생성되도록 한다. 그리고, 캐리어 소오스층(17)은 상기 이동 통로인 2차원 전자 기체(21)에 전자를 공급하는 것으로 실리콘 등의 N형 불순물이 도핑된 AlGaAs로 형성된다. 상기에서 2차원 전자기체(21)의 전자밀도는 캐리어 소오스층(17)의 도핑농도와 그 두께에 의하여 결정된다. 또한, 캡층(19)은 불순물이 도핑되지 않은 GaAs로 형성된다.The buffer layer 13 is formed of GaAs that is not doped with impurities to prevent diffusion of crystal defects and the like of the semiconductor substrate 11. The spacer 15 is formed of AlGaAs having an energy band gap larger than that of GaAs forming the buffer layer 13 which is not doped with impurities, and thus the two-dimensional electron gas 21 that becomes a movement path for electrons and superconducting currents in the buffer layer 13. Will be generated. The carrier source layer 17 supplies electrons to the two-dimensional electron gas 21 serving as the movement path, and is formed of AlGaAs doped with N-type impurities such as silicon. The electron density of the two-dimensional electromagnetic body 21 is determined by the doping concentration of the carrier source layer 17 and its thickness. In addition, the cap layer 19 is formed of GaAs which is not doped with impurities.
제2(b)도를 참조하면, 상기 캡층(19)의 상부에 포토레지스트(Photo-resist:도시되지 않음)을 얇게 입힌 후, 포토리쏘그라피(Photo-Lithography) 방법에 의해 포토레지스트의 소자모양(pattern)을 형성한 후, 순(順) 메사에칭(Mesa Etching)을 하고 포토레지스트를 제거한다. 상기 순 메사에칭 공정시 반도체기판(11)도 에칭되도록 한다.Referring to FIG. 2 (b), after the photoresist (not shown) is thinly coated on the cap layer 19, the device shape of the photoresist is formed by a photo-lithography method. After the pattern is formed, Mesa etching is performed and the photoresist is removed. The semiconductor substrate 11 is also etched during the net mesa etching process.
제2(c)도를 참조하면, 상술한 구조의 전표면에 포토레지스트(도시되지 않음)을 코팅하고 통상의 포토기술에 의하여 캡층(19)이 상부를 제외한 메사양옆의 포토레지스트를 선택적으로 제거한다. 그리고, 노출된 측면에 초전도 박막 형성장치(예를 들어, 스퍼터링 장치 혹은 레지저 애블레이션 장치를 이용하여 초전도 박막을 코팅하여 소오스 및 드레인전극(23)(25)을 형성시킨다. 그 다음, 포토레지스트를 제거하고 통상의 리프트 오프(lift-off) 방법에 의해 게이트 전극(27)을 형성한다.Referring to FIG. 2 (c), a photoresist (not shown) is coated on the entire surface of the above-described structure, and the photoresist next to the mesa except for the upper portion of the cap layer 19 is selectively removed by a conventional photo technique. do. Then, the superconducting thin film is coated on the exposed side by using a superconducting thin film forming apparatus (for example, a sputtering apparatus or a resist ablation apparatus) to form source and drain electrodes 23 and 25. Then, photoresist Is removed and the gate electrode 27 is formed by a conventional lift-off method.
이상과 같은 공정을 거친 후 완성된 전계효과 트랜지스터의 모양은 제1도에 잘 나타나 있다.The shape of the field effect transistor completed after the above process is well shown in FIG.
상기 게이트 전극(27)에 전압을 걸어주어 버퍼층(13)과 스페이서층(15)의 이종접합부분에 형성된 2차원 전자 기체(21)의 밴드의 휨(band bending)을 조절하면, 2차원 전자기체(21)의 전자밀도가 변하게 된다.When the voltage is applied to the gate electrode 27 to adjust the band bending of the two-dimensional electron gas 21 formed at the heterojunction of the buffer layer 13 and the spacer layer 15, the two-dimensional electromagnetic body The electron density of (21) changes.
이에 따라 이종접합면을 따라 흘러가는 초전도 전류(supercurrent)의 양이 조절되어, 제3도와 같은 전류전압의 특성을 나타내게 된다.Accordingly, the amount of superconducting current (supercurrent) flowing along the heterojunction surface is controlled to exhibit the characteristics of the current voltage as shown in FIG.
이러한 구조의 트랜지스터를 조셉스 접합 전계효과 트랜지스터 또는 초전도 전류전계효과 트랜지스터(supercurrent field effect transisor)라고 한다.Such a transistor is called a Joseph's junction field effect transistor or a superconducting current field effect transistor.
본 발명에 따른 조셉슨 접합 전계효과 트랜지스터는 수 ps의 스위칭 시간, 수 μW의 소모전력, 그리고 100mS/mm 이상의 상호 콘덕턴스(transconductance)를 갖게 되며, 소오스-드레인 간에 전위차가 없을때도 초전도 전류가 흐르기 때문에, 종래의 여러 형태의 트랜지스터의 특성을 포함한 새로운 영역의 트랜지스터 소자로의 응융이 가능하게 된다.The Josephson junction field effect transistor according to the present invention has a switching time of several ps, a power consumption of several μW, and a transconductance of 100 mS / mm or more, and superconducting current flows even when there is no potential difference between the source and drain. It is possible to solidify the transistor element in a new area including the characteristics of various conventional transistors.
더구나 접합부분으로 반도체 2차원 전자기체층을 쓰기때문에 이미 확립된 최점단의 반도체 기술을 그대로 도입하여 신뢰성있는 전자소자의 구현이 가능할 뿐 아니라, 반도체 기판위에서 모든 공정이 이루어지므로 다른 연관된 소자간의 연결에 이상적이며, 이와같은 소자들의 고집적화에도 매우 유리하다.Moreover, since the semiconductor two-dimensional electromagnetic layer is used as the junction, it is possible to implement reliable electronic devices by adopting the most advanced semiconductor technology that has already been established. Ideally, it is also very advantageous for high integration of such devices.
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| KR1019920020985A KR950011032B1 (en) | 1992-11-10 | 1992-11-10 | Josephson junction field effect transistor and its making method |
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| KR1019920020985A KR950011032B1 (en) | 1992-11-10 | 1992-11-10 | Josephson junction field effect transistor and its making method |
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