KR950010347A - Automatic Gain Control Circuit by DC Offset Voltage - Google Patents

Automatic Gain Control Circuit by DC Offset Voltage Download PDF

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Publication number
KR950010347A
KR950010347A KR1019930018110A KR930018110A KR950010347A KR 950010347 A KR950010347 A KR 950010347A KR 1019930018110 A KR1019930018110 A KR 1019930018110A KR 930018110 A KR930018110 A KR 930018110A KR 950010347 A KR950010347 A KR 950010347A
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KR
South Korea
Prior art keywords
upper limit
signal
limit peak
value
lower limit
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KR1019930018110A
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Korean (ko)
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KR100191304B1 (en
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정원석
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김광호
삼성전자 주식회사
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Priority to KR1019930018110A priority Critical patent/KR100191304B1/en
Publication of KR950010347A publication Critical patent/KR950010347A/en
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Publication of KR100191304B1 publication Critical patent/KR100191304B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G11/00—Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
    • H03G11/08—Limiting rate of change of amplitude
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
    • H03G1/0029—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier using FETs

Abstract

본 발명은 신호를 증폭 및 전송할 때 직류오프셋전압에 의해 신호의 일부가 전원전압의 스윙폭을 넘어가 차단되는 것을 방지하기 위해 자동으로 이득을 감소시켜 신호를 안정되게 전송할 수 있도록 한 직류오프셋전압에 의한 자동이득 조절회로에 관한 것이다. 이와 같은 본 발명의 자동이득조절회로는 증폭부에서 출력된 신호의 상한피크값과 하한피크값을 검출하여 동작전원의 상한값 및 하한값과 비교하는 상한피크 검출수단 및 하한피크 검출수단과, 상기 상한피크 검출수단 및 하한피크 검출수단의 출력신호에 따라 증폭부의 궤환저항값을 가변시켜 증폭률을 변화시키는 전압제어저항부를 구비하게 된다. 따라서, 전송신호의 일부가 전원전압의 상한값 또는 하한값을 초과하는 경우에는 원래의 신호를 정확히 전송할 수 있는 효과가 있다.According to the present invention, when amplifying and transmitting a signal, a DC offset voltage is automatically reduced so that a part of the signal is cut off beyond the swing width of the power voltage by the DC offset voltage. It relates to an automatic gain control circuit. As described above, the automatic gain control circuit of the present invention detects an upper limit peak value and a lower limit peak value of a signal output from an amplifying unit, and compares the upper limit peak detection means and the lower limit peak detection means with the upper limit value and the lower limit value of the operating power supply, and the upper limit peak. And a voltage control resistor for varying the amplification ratio by varying the feedback resistance of the amplifier in accordance with the output signal of the detection means and the lower limit peak detection means. Therefore, when a part of the transmission signal exceeds the upper limit value or the lower limit value of the power supply voltage, the original signal can be accurately transmitted.

Description

직류오프셋전압에 의한 자동이득 조절회로Automatic Gain Control Circuit by DC Offset Voltage

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 직류오프셋전압에 의한 자동이득조절회로의 블록구성도.3 is a block diagram of an automatic gain control circuit based on a DC offset voltage according to the present invention.

제4도는 제3도에 따른 직류오프셋전압에 의한 자동이득조절회로의 구체적인 실시예를 나타내는 회로도.4 is a circuit diagram showing a specific embodiment of the automatic gain control circuit by the DC offset voltage according to FIG.

Claims (7)

소정의 증폭률로 입력시호를 증폭하여 전송하는 증폭장치에 있어서, 상기 증폭장치에서 출력된 신호의 상한피크값을 검출하여 동작전원의 상한값과 비교하는 상한피크 검출수단과; 상기 증폭장치에서 출력된 신호의 하한피크값을 검출하여 동작전원의 하한값과 비교하는 하한피크 검출수단과; 상기 상판피크 검출수단과 하한피크 검출수단의 출력신호를 논리합하는 논리소자와; 상기 논리소자의 출력신호에 따라 상기 증폭장치의 궤환저항값을 가변시켜 증폭률을 변화시키는 전압제어저항부를 포함하는 것을 특징으로 하는 직류오프셋전압에 의한 자동이득조절회로.An amplifying apparatus for amplifying and transmitting an input signal at a predetermined amplification rate, the amplifying apparatus comprising: an upper limit peak detecting means for detecting an upper limit peak value of a signal output from the amplifying apparatus and comparing it with an upper limit value of an operating power source; Lower limit peak detection means for detecting a lower limit peak value of the signal output from the amplifier and comparing it with a lower limit value of an operating power supply; A logic element for logically combining the output signals of the upper peak detection means and the lower limit peak detection means; And a voltage control resistor for varying the amplification ratio by varying the feedback resistance value of the amplifier according to the output signal of the logic element. 제1항에 있어서, 상기 상한피크 검출수단은 상기 증폭장치에서 출력된 신호의 상한피크 값을 검출하는 상한피크 검출부와; 상기 상한피크 검출부의 출력신호와 동작전원의 상한값을 비교, 감산하는 제1 감산부와; 제1 감사부의 출력신호를 논리소자의 동작전압에 맞도록 논리 1 또는 0 상태로 출력하는 제1 비교부로 구성하는 것을 특징으로 하는 직류오프셋전압에 의한 자동이득조절회로.2. The apparatus of claim 1, wherein the upper limit peak detection means comprises: an upper limit peak detector for detecting an upper limit peak value of a signal output from the amplifying apparatus; A first subtraction unit for comparing and subtracting an output signal of the upper limit peak detection unit with an upper limit value of an operating power source; And a first comparator for outputting an output signal of the first auditor to a logic 1 or 0 state in accordance with an operating voltage of the logic element. 제2항에 있어서, 상기 상한피크 검출부는 증폭장치의 출력신호를 입력받는 제1증폭기와; 제1증폭기의 입출력단에 순방향으로 연결되어 정극성신호만을 통과시키는 제1, 제2다이오드와; 제2다이오드를 거친 신호를 충전하여 소정시간동안의 상한피크값을 검출하는 콘덴서와; 상기 상한피크값을 입력받아 버퍼로 동작하는 제2증폭기와; 상기 콘덴서 양단에 연결되어 상한피크값을 검출하는 시간을 설정하는 스위치를 포함하는 것을 특징으로 하는 직류오프셋전압에 의한 자동이득조절회로.3. The apparatus of claim 2, wherein the upper limit peak detector comprises: a first amplifier configured to receive an output signal of an amplifying apparatus; First and second diodes connected in a forward direction to an input and output terminal of the first amplifier and passing only a positive signal; A capacitor which charges a signal passed through the second diode to detect an upper peak value for a predetermined time; A second amplifier configured to receive the upper limit peak value and operate as a buffer; And a switch connected to both ends of the capacitor to set a time for detecting an upper limit peak value. 제1항에 있어서, 상기 하한피크 검출수단은 상기 증폭장치에서 출력된 신호의 하한피크값을 검출하는 하한피크 검출부와; 상기 하한피크 검출부의 출력신호와 동작전원의 하한값을 비교, 감산하는 제2 감산부와; 제2 감산부의 출력신호를 논리소자의 동작전압에 맞도록 놀리 1 또는 0상태로 출력하는 제2 비교부로 구성하는 것을 특징으로 하는 직류오프셋전압에 의한 자동이득조절회로.The low limit peak detection unit of claim 1, further comprising: a lower limit peak detection unit for detecting a lower limit peak value of a signal output from the amplifier; A second subtraction unit for comparing and subtracting an output signal of the lower limit peak detection unit with a lower limit value of an operating power source; And a second comparator for outputting the output signal of the second subtractor in a no. 1 or 0 state to match the operating voltage of the logic element. 제4항에 있어서, 상기 하한피크 검출부는 증폭장치의 출력신호를 입력받는 제3증폭기와; 제3증폭기의 입출력단에 역방향으로 연결되어 부극성신호만을 통과시키는 제3, 제4다이오드와; 제4다이오드를 거친 신호를 충전하여 소정시간동안의 하한피크값을 검출하는 콘덴서와; 상기 하한피크값을 입력받아 버퍼로 동작하는 제4증폭기와; 상기 콘덴서 양단에 연결되어 하한피크값을 검출하는 시간을 설정하는 스위치를 포함하는 것을 특징으로 하는 직류오프셋전압에 의한 자동이득조절회로.5. The apparatus of claim 4, wherein the lower peak detection unit comprises: a third amplifier receiving an output signal of the amplifying apparatus; Third and fourth diodes connected to the input / output terminals of the third amplifier in a reverse direction to pass only the negative signal; A capacitor which charges a signal passed through the fourth diode to detect a lower peak value for a predetermined time; A fourth amplifier configured to receive the lower peak value and operate as a buffer; And a switch connected to both ends of the capacitor to set a time for detecting a lower peak value. 제1항에 있어서, 상기 전압제어저항부는 상기 논리소자의 출력신호를 소정레벨로 강하시키기 위해 연결한 질류전원과; 상기 직류전원에 의해 강하된 게이트전압에 따라 동작하여 저항값이 가변되는 접합형 전계효과트랜지스터를 포함하는 것을 특징으로 하는 직류오프셋전압에 의한 자동이득조절회로.2. The apparatus of claim 1, wherein the voltage control resistor unit comprises: a galvanic power source connected to drop the output signal of the logic element to a predetermined level; And a junction type field effect transistor having a variable resistance value by operating in response to a gate voltage dropped by the DC power supply. 제6항에 있어서, 상기 접합형 전계효과트랜지스터는 오믹영역에서 동작되도록 드레인전압을 낮은 레벨로 공급하도록 한 것을 특징으로 하는 질류오프셋전압에 의한 자동이득조절회로.7. The automatic gain control circuit according to claim 6, wherein the junction field effect transistor is configured to supply a drain voltage at a low level to operate in an ohmic region. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930018110A 1993-09-09 1993-09-09 Agc circuit for dc offset voltage KR100191304B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930018110A KR100191304B1 (en) 1993-09-09 1993-09-09 Agc circuit for dc offset voltage

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Application Number Priority Date Filing Date Title
KR1019930018110A KR100191304B1 (en) 1993-09-09 1993-09-09 Agc circuit for dc offset voltage

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KR950010347A true KR950010347A (en) 1995-04-28
KR100191304B1 KR100191304B1 (en) 1999-06-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100902886B1 (en) * 2009-03-02 2009-06-16 주식회사동원프라스틱 A coupler for connecting water pipe

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100902886B1 (en) * 2009-03-02 2009-06-16 주식회사동원프라스틱 A coupler for connecting water pipe

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