KR950010210A - Semiconductor device and manufacturing method - Google Patents

Semiconductor device and manufacturing method Download PDF

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Publication number
KR950010210A
KR950010210A KR1019930019947A KR930019947A KR950010210A KR 950010210 A KR950010210 A KR 950010210A KR 1019930019947 A KR1019930019947 A KR 1019930019947A KR 930019947 A KR930019947 A KR 930019947A KR 950010210 A KR950010210 A KR 950010210A
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South Korea
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axis direction
patterns
semiconductor device
pattern
interval
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KR1019930019947A
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Korean (ko)
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KR970005167B1 (en
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박재관
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김광호
삼성전자 주식회사
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Priority to KR1019930019947A priority Critical patent/KR970005167B1/en
Priority to JP6172552A priority patent/JPH07169852A/en
Publication of KR950010210A publication Critical patent/KR950010210A/en
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Publication of KR970005167B1 publication Critical patent/KR970005167B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

신규한 종형 전극배선층의 연결방법이 개시되어 있다. X축방향으로 제1간격을 두고 일렬로 형성되고, 상기 X축 방향과는 수직인 Y축 방향으로 제2간격으로 형성되어 다수의 열을 이루고 있는 패턴들; 및 상기 패턴들을 둘러 싸고 있으며, 상기 Y축 방향의 상기 패턴들 사이의 공간은 도전성 물질로 매립되어 있는 도전성 구조물을 포함하는 반도체 장치가 제공된다.A novel method of connecting the vertical electrode wiring layer is disclosed. Patterns formed in a row with a first interval in the X-axis direction and formed in a second interval in the Y-axis direction perpendicular to the X-axis direction to form a plurality of rows; And a conductive structure surrounding the patterns, wherein a space between the patterns in the Y-axis direction is filled with a conductive material.

별도의 사진공정이나 연결용 도전층 없이, 종형의 전극배선층들을 용이하게 연결할 수 있다.It is possible to easily connect the vertical electrode wiring layers without a separate photo process or a conductive layer for connection.

Description

반도체장치 및 그 제조방법Semiconductor device and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명에 의해 제조된 종형 게이트전극 배선의 개략적인 사시도,5 is a schematic perspective view of a vertical gate electrode wiring manufactured by the present invention;

제6도는 본 발명에 의한 실리콘 필라의 평면도,6 is a plan view of a silicon pillar according to the present invention,

제7A-B도 내지 제9A-B도는 본 발명에 의한 종형 게이트 전극 배선의 연결방법을 설명하기 위한 단면도들,7A-B to 9A-B are cross-sectional views illustrating a method of connecting a vertical gate electrode wiring according to the present invention;

제10도는 본 발명에 의해 제조된 종형 게이트전극 배선의 평면도.10 is a plan view of a vertical gate electrode wiring manufactured according to the present invention.

Claims (13)

X축 방향으로 제1간격을 두고 일렬로 형성되고, 상기 X축 방향과는 수직인 Y축 방향으로 제2간격으로 형성되어 다수의 열을 이루고 있는 패턴들; 및 상기 패턴들을 둘러 싸고 있으며, 상기 Y축 방향의 상기 패턴들 사이의 공간은 도전성 물질로 매립되어 있는 도전성 구조물을 포함하는 반도체 장치.Patterns formed in a row with a first interval in the X-axis direction and formed in a second interval in the Y-axis direction perpendicular to the X-axis direction to form a plurality of rows; And a conductive structure surrounding the patterns, wherein a space between the patterns in the Y-axis direction is filled with a conductive material. 제1항에 있어서, 상기 패턴들간의 제2간격은 상기 제1간격보다 좁게 형성된 것을 특징으로 하는 반도체 장치.The semiconductor device of claim 1, wherein a second gap between the patterns is formed to be narrower than the first gap. 제1항에 있어서, 상기 패턴들은, 반도체 기판 상부에 형성되며 그 상부에 트랜지스터가 형성되는 실리콘 필라들인 것을 특징으로 하는 반도체 장치.The semiconductor device of claim 1, wherein the patterns are silicon pillars formed on the semiconductor substrate and having transistors formed thereon. 제3항에 있어서, 상기 필라를 보호하기 위하여 상기 필라 상에 형성되어 있는 절연막 패턴을 더 포함하는 것을 특징으로 하는 반도체 장치.4. The semiconductor device of claim 3, further comprising an insulating film pattern formed on the pillar to protect the pillar. 제3항에 있어서, 상기 필라의 측벽 상에는 게이트산화막이 형성되어 있는 것을 특징으로 하는 반도체 장치.4. The semiconductor device according to claim 3, wherein a gate oxide film is formed on sidewalls of the pillars. 제1항에 있어서, 상기 도전성 구조물은 워드라인인 것을 특징으로 하는 반도체 장치.The semiconductor device of claim 1, wherein the conductive structure is a word line. 제1항에 있어서, 상기 도전성 구조물은 상기 패턴의 상부표면을 노출시킨 것을 특징으로 하는 반도체 장치.The semiconductor device of claim 1, wherein the conductive structure exposes an upper surface of the pattern. 평면상의 X축 방향으로는 제1간격을 가지고, 상기 X축 방향에 수직인 Y축 방향으로는 상기 제1간격보다 좁은 제2간격을 가지도록 패턴들을 형성하는 단계; 상기 패턴들이 형성된 결과물 상에 도전성 물질을 침적하여 상기 패턴들 사이의 Y축 방향의 공간은 매립하고, X축 방향의 공간에는 그루브를 갖는 도전층을 형성하는 단계; 및 상기 도전층을 이방성 식각하여, 상기 패턴들을 각각 둘러싸고, 상기 Y축 방향으로는 상호 연결되고, 상기 X축 방향으로는 상호 분리되고, 상기 Y축 방향의 상기 패턴들 사이의 공간을 매립하는 도전성 구조물을 형성하는 단계를 구비하는 것을 특징으로 하는 반도체 장치의 제조방법.Forming patterns having a first interval in the X-axis direction on the plane and a second interval narrower than the first interval in the Y-axis direction perpendicular to the X-axis direction; Depositing a conductive material on the resultant product on which the patterns are formed to fill a space in the Y-axis direction between the patterns and form a conductive layer having a groove in the space in the X-axis direction; And anisotropically etch the conductive layer to surround the patterns, interconnect with each other in the Y-axis direction, separate each other with the X-axis direction, and fill a space between the patterns in the Y-axis direction. And forming a structure. 제8항에 있어서, 상기 이방성 식각은 상기 패턴의 상부 표면을 노출할 때까지 수행하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of claim 8, wherein the anisotropic etching is performed until the top surface of the pattern is exposed. 제8항에 있어서, 상기 패턴들은, 반도체 기판을 식각하여 형성되는 실리콘 필라들인 것을 특징으로 하는 반도체 장치의 제조방법.The method of claim 8, wherein the patterns are silicon pillars formed by etching a semiconductor substrate. 제8항에 있어서, 상기 패턴을 보호하기 위하여 상기 패턴상에 절연막 패턴을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치.The semiconductor device according to claim 8, further comprising forming an insulating film pattern on the pattern to protect the pattern. 제8항에 있어서, 상기 도전층을 형성하는 단계 전에, 상기 패턴의 측벽상에 절연막을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.10. The method of claim 8, further comprising forming an insulating film on sidewalls of the pattern before forming the conductive layer. 제8항에 있어서, 상기 도전층은 상기 패턴들 사이의 Y축 방향의 공간은 매립할 수 있는 정도의 두께로 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of claim 8, wherein the conductive layer is formed to a thickness such that the space in the Y-axis direction between the patterns is buried. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930019947A 1993-09-27 1993-09-27 A method of manufacturing for semiconductor KR970005167B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019930019947A KR970005167B1 (en) 1993-09-27 1993-09-27 A method of manufacturing for semiconductor
JP6172552A JPH07169852A (en) 1993-09-27 1994-07-25 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930019947A KR970005167B1 (en) 1993-09-27 1993-09-27 A method of manufacturing for semiconductor

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KR950010210A true KR950010210A (en) 1995-04-26
KR970005167B1 KR970005167B1 (en) 1997-04-12

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KR970005167B1 (en) 1997-04-12
JPH07169852A (en) 1995-07-04

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