KR950008279Y1 - Error condition display of watchdog circuit - Google Patents

Abstract

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Description

Error status display device of watchdog circuit

1 is a detailed circuit diagram of a conventional watchdog circuit.

2 is an operation waveform diagram of a main part of a conventional watchdog circuit.

3 is a detailed circuit diagram of an error state display device of the watchdog circuit according to the embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

11, 12, 13: 1st, 2nd, 3rd stage stable multivibrator

G11, G34: Inverter

G12, G13: NOR gate G13: NAND gate

Q11, Q12, Q31, Q32: transistors D11, D12, D31, D32: light emitting diodes

The present invention relates to an error status display device of a watchdog circuit, and more specifically, an error of a watchdog circuit that clearly indicates an error state so that a user can easily see what kind of error has occurred. It relates to a status display device.

In general, a computer system using a microprocessor includes a timer that is a monitoring device for detecting an abnormal operation of hardware or software. Such a timer is called a watchdog circuit.

For reference, the above description of the watchdog circuit is described in Korean Utility Model Application Publication No. 92-8354 (Application Date: July 7, 1990), or Publication No. 93- "Watchdog Circuit" in 2226 (filed September 7, 1990) or "Watchdog Circuit" in Publication No. 93-1397 (Application: October 24, 1990). .

Hereinafter, a conventional watchdog circuit will be described with reference to the accompanying drawings.

1 is a detailed circuit diagram of a conventional watchdog circuit, and FIG. 2 is an operation waveform diagram of a main part of the conventional watchdog circuit.

As shown in FIG. 1, the structure of the conventional watchdog circuit includes a first terminal in which a clear terminal / CLR is connected to the power supply voltage Vcc through a resistor R11, and the input terminal / A is grounded. A monostable multivibrator 11, an inverter G11 having an input terminal connected to a power supply signal line PON, an output terminal of the inverter G11, and an output terminal Q of the first single-stable multivibrator 11 NOR gate (G12) and input terminal (B) are connected to the operation state signal line (FRESH). A NAND gate G13 having an input terminal connected to an inverted output terminal / Q of the second single-stable multivibrator 12 and the NOR gate G12 and the second single-stable multivibrator 12, and a NAND gate Resistor R13 and capacitor C11 connected in series between the output terminal of G13 and ground, and the NOR gate G12. The clear terminal (/ CLR) is connected to the output terminal, the input terminal (B) is connected to the connection point of the resistor (R13) and the capacitor (C11), the input terminal (/ A) is grounded, and the inverted output terminal (/ Q ) Is a third single-stable multivibrator 13 and a third single-stable multivibrator 13 that are feedbacked to the input terminals B and / A of the first and second single-stable multivibrators 11 and 12, respectively. The transistors Q11 and Q12 and the collector terminals of the transistors Q11 and Q12 are connected to the output terminals Q and / Q through the resistors R14 and R16, respectively, and the emitter terminals are grounded. And diodes D11 and D12 and resistors R15 and R17 that are forward connected in series, respectively, between the power supply voltage Vcc.

The first to third monostable multivibrators 11 to 13 use a dual retriggerable monostable multivibrator with clear (KS74AHCT123) chip.

(Function table)

The operation of the conventional watchdog circuit constructed as described above is as follows.

When the power supply voltage Vcc is applied, the watchdog circuit periodically generates an operating state signal FRESH as shown in section (a) of FIG. 3 when the microprocessor is operating normally from a microprocessor (not shown). The operation of the watchdog circuit is started by inputting.

The power supply signal PON remains high when power is normally supplied, and goes low when power supply is stopped. Therefore, when the power is normally supplied, the low state signal is output from the inverter G11.

In the first stage stable multivibrator 11, a high signal is input to the clear terminal (/ CLR), a low signal is input to the input terminal (/ A), and a low signal is input to the input terminal (B). Since the signal is being input, the output terminal Q outputs the low signal C when referring to the above <function table>.

When a low state signal is input from the output terminal Q of the inverter G11 and the first stage stable multivibrator 11, the output signal D of the NOR gate G12 becomes a high state.

Since the signal of the high state is input to the clear terminal (/ CLR) and the signal of the low state is input to the input terminal (/ A), the second single-stable multivibrator 12 refers to the above <function table>. When the rising edge of the operation state signal FRESH input to the input terminal B is output, the low state signal is output to the inverted output terminal / Q for a predetermined period.

The signal E output from the inverted output terminal / Q of the second single-stable multivibrator 12 is inverted by the NAND gate G13 and then the input terminal (3) of the third single-stable multivibrator 13. Is output to B). At this time, the output signal of the NAND gate G13 is removed by the capacitor C11 and the waveform is shaped at the same time.

Since the high level signal is input to the clear terminal (/ CLR) and the low level signal is input to the input terminal (/ A), the third stage stable multivibrator 12 refers to the above <function table>. When the rising edge of the output signal of the NAND gate G13 input to the input terminal B is output, the low-state signal is output to the inverting output terminal / Q for a predetermined period.

At this time, before the low state signal output from the inverting output terminal (/ Q) of the third stage stable multivibrator 13 becomes high, the input terminal B of the third stage stable multivibrator 13 Since the pulse signal is again input from the NAND gate G13, the inverting output terminal / Q of the third single-stable multivibrator 13 remains low.

Therefore, when the microprocessor is operating normally, the transistor Q11 is turned on so that the light emitting diode D11 emits light, and the transistor Q12 is turned off so that the light emitting diode D12 does not emit light.

As such, the overall operating state of the watchdog circuit is shown in detail in section (a) of FIG.

When the microprocessor is not operating normally, i.e. when the program is in error or the CPU or memory is damaged, the high state of operation as shown in section (b) of FIG. 3 from the microprocessor. The signal FRESH is input to the watchdog circuit.

When the high state operation state signal FRESH is input to the input terminal B, the second single-stable multivibrator 12 receives the high state signal to the clear terminal / CLR and the input terminal / A. Since the low state signal is being input, referring to the above <function table>, the high state signal E is continuously maintained.

When the inverted output terminal (/ Q) of the second single-stable multivibrator 12 remains high, the third single-stable multivibrator 13 keeps the output signal of the NAND gate G13 continuously low. It is output to the input terminal B of.

When the low signal is continuously input to the input terminal B, the third stage stable multivibrator 13 receives the high terminal signal after a predetermined time has elapsed since the rising edge signal ↑ was input. Output (F) to the inverting output terminal (/ Q).

When the high-state signal F is input from the output terminal Q of the third stage stable multivibrator 13 to the input terminal B, the first stage stable multivibrator 11 goes to the clear terminal / CLR. Since the high state signal is being input and the low state signal is being input to the input terminal (/ A), referring to the <function table>, the output terminal Q outputs the pulse signal C for a predetermined period. .

The pulse signal C of the first single-stable multivibrator 11 is inverted through the NOR gate G12 and then output to the clock terminal / CLR of the second single-stable multivibrator 12.

The second single-stable multivibrator 12 inverts the signal E in the low state at the rising edge of the output signal D of the NOR gate G12 input to the clear terminal / CLR. Will output

In addition, the third stage stable multivibrator 13 inverts the signal F in the low state at the rising edge of the output signal D of the NOR gate G12 input to the clear terminal / CLR. )

When a low signal is continuously input from the NAND gate G13 to the input terminal B of the third stage stable multivibrator 13, the signal rises to the input terminal B of the third stage stable multivibrator 13. When a predetermined time has elapsed since the input of the corner signal ↑, the above-described operation is repeatedly performed by outputting the high state signal F of the third stage stable multivibrator 13 to the inverting output terminal / Q.

Therefore, when the microprocessor is not normally operated, that is, when the program is in error or the central processing unit or the memory is damaged, the transistors Q11 and Q12 are repeatedly complementary to each other to turn on / off the light. The diodes D11 and D12 flash complementarily with each other.

The overall operating state of the watchdog circuit operated in this manner is shown in detail in section (b) of FIG.

In the case where the power is not properly supplied, the power supply signal PON goes low, as shown in section (c) of FIG.

When the power supply signal PON goes low, the output signal of the inverter G11 goes high, so the output signal D of the NOR gate G12 goes low.

Since the output signal D in the low state of the NOR gate G12 is applied to the clear terminal / CLR of the second and third single-stable multivibrators 12 and 13, respectively, referring to the above <function table> The second and third monostable multivibrators 12 and 13 output the high state signal to the inverted output terminal / Q regardless of the signal input to the other input terminals / A and B.

Therefore, when the power is not normally supplied, the transistor Q11 is turned off so that the light emitting diode D11 does not emit light, and the transistor Q12 is turned on so that the light emitting diode D12 emits light.

Such an overall operating state of the watchdog circuit is shown in detail in section (C) of FIG.

However, the above-described conventional watchdog circuit distinguishes an error state (microprocessor abnormal operation, power supply interruption) through the flashing state of the light emitting diodes D11 and D12, so that the light emitting diodes D11 and D12 according to the type of error are used. For those who are not aware of the flashing state of the type of error has a disadvantage that can not easily know.

Accordingly, an object of the present invention is to solve the above-mentioned disadvantages, and provides an error state display device of a watchdog circuit that clearly displays the state of an error so that a user can easily recognize what kind of error has occurred. It is.

In order to achieve the above object, the constitution of the present invention is to output a low state signal to an output terminal when a watchdog signal in a low state is input, and a high state signal to an output terminal when a watchdog signal in a pulse state is input. Outputs a high-stable watchdog signal, and a monostable multivibrator continuously outputs a low signal to an output terminal, a signal input from an output terminal of the monostable multivibrator, and a watchdog signal. As a result, an OR gate for outputting a result signal, a first AND gate for performing an AND operation on the signal input from the inverted output terminal of the monostable multivibrator and a watchdog signal, and outputting the resultant signal; A second AND gate for outputting the AND signal by multiplying the output signal and the signal input from the first AND gate A first AND second transistor turned on and off by an inputted inverter, a third AND gate for performing an AND operation on the OR gate and a signal input from the inverter, and a signal input from the second and third AND gates, respectively. And first and second light emitting diodes displaying the state of an error by emitting light as the first and second transistors are turned on and off.

By the above configuration, the most preferred embodiment which can be easily carried out by those skilled in the art to which this invention belongs will be described in detail with reference to the accompanying drawings.

3 is a detailed circuit diagram of an error state display device of the watchdog circuit according to an embodiment of the present invention, and FIG. 4 is an operation waveform diagram of a main part of the error state display device of the watchdog circuit according to an embodiment of the present invention.

As shown in FIG. 3, the configuration of the error state display device of the watchdog circuit according to the embodiment of the present invention includes a pullup resistor R31 connected between the watchdog signal line F and the power supply voltage Vcc. , The capacitor C31 connected between the watchdog signal line F and the ground, the input terminal B is connected to the watchdog signal line F, and the clear terminal / CLR is connected to the power supply voltage Vcc. The input terminal / A is connected to the monostable multivibrator 31 and the output terminal Q and the watchdog signal line F of the monostable multivibrator 31, respectively. OR gate (G31), AND gate (G32) and OR gate (G31), each having an input terminal connected to the inverted output terminal (/ Q) and watchdog signal line (F) of the monostable multivibrator (31). And an output terminal of the AND gate G33 and an AND gate G32 having an input terminal connected to an output terminal of the AND gate 32, respectively. Inverter G34 to which input terminals are connected, AND gate G35 to which input terminals are connected to output terminals of OR gate G31 and inverter G34, and output terminals of AND gates G33 and G35, respectively. Resistors (R33 and R34) having one terminal connected to each other, a base terminal connected to the other terminal of the resistors (R33 and R34), respectively, and an emitter terminal having grounds (Q31 and Q32), The resistors R32 and R35 having one terminal connected to the power supply voltage Vcc and the anode terminals thereof are connected to the other terminals of the resistors R32 and E35 respectively and the cathodes of the collector terminals of the transistors Q31 and Q32 are connected. The light emitting diodes D31 and D32 are connected to terminals, respectively.

In the embodiment of this invention, the KS74AHCT123 chip is used as the above-mentioned monostable multivibrator 31, but the technical scope of this invention is not limited thereto.

The input / output operation of the KS74AHCT123 chip is performed as in the <function table> as mentioned above.

The operation of the error status display device of the watchdog circuit according to the embodiment of the present invention by the above configuration is as follows. When the power supply Vcc is applied, the operation of the error status display device of the watchdog circuit according to the embodiment of the present invention is started.

When the microprocessor is operating normally and the power is normally supplied, the low-level watchdog signal F as shown in the section in FIG. 2A receives the input terminal B of the monostable multivibrator 31. At the same time, the input terminal is input to the AND gate G32.

The watchdog signal F described above uses the output signal of the collector terminal of the transistor Q11 shown in the first, and the output signal of the collector terminal of the transistor Q11 as shown in the circuit diagram of FIG. It has the same waveform as the signal F output from the inverting output terminal / Q of the third single-stable multivibrator 13. When the watchdog signal F in the low state is input to the input terminal B, the monostable multivibrator 31 receives the high state signal through the clear terminal (/ CLR) and goes low to the input terminal (/ A). Since the state signal is being input, referring to the above <function table>, the low state signal is output to the output terminal Q to the OR gate G31, and the high state signal to the inverted output terminal (/ Q). Is output to the AND gate G32.

Therefore, since the outputs of the OR gate G31 and the AND gate G32 are in a low state, the outputs of the AND gates G33 and G35 are in a low state, and both the transistors Q31 and Q32 are turned off. When the transistors Q31 and Q32 are both turned off, the light emitting diodes D31 and S32 do not emit light, indicating that the microprocessor is operating normally and power is normally supplied.

When the power is normally supplied but the microprocessor is operating abnormally, the watchdog signal F in the pulse state as shown in the section in FIG. 2B is the input terminal B of the monostable multivibrator 31. At the same time it is input to the AND terminal G32.

When the watchdog signal F in the pulse state is input to the input terminal B, the monostable multivibrator 31 receives the high signal through the clear terminal (/ CLR) and goes low to the input terminal (/ A). Since the state signal is being input, referring to the above <function table>, the high state signal is output to the output terminal Q to the OR gate G31 and the low state signal to the inverted output terminal (/ Q). Is output to the AND gate G32.

In this case, since the pulse holding period of the output terminal Q is designed to be longer than the period of the watchdog signal F, the above-mentioned monostable multivibrator 31 is inputted. The output terminal Q of the monostable multivibrator 31 is always kept high and the inverted output terminal / Q is always kept low.

When the high state signal is input from the output terminal Q of the monostable multivibrator 31, the OR gate G31 outputs the high state output signal to the AND gates G33 and G35.

When the low state signal is input from the inverting output terminal / Q of the monostable multivibrator 31, the AND gate G32 outputs the low state output signal to the AND gate G33 and the inverter G34. When the low state signal is input from the AND gate G32, the AND gate G33 outputs the low state signal to the base terminal of the transistor Q31, and the inverter G34 outputs the high state signal to the AND gate G35. ) When the high state signal is input from the OR gate G31 and the inverter G34, the AND gate G35 outputs the high state signal to the base terminal of the transistor Q32.

Accordingly, transistor Q31 is turned off and transistor Q32 is turned on.

Since the light emitting diode D31 does not emit light when the transistor Q31 is turned off, and the light emitting diode D32 emits light when the transistor Q32 is turned on, power is normally supplied, but the microprocessor is in abnormal operation. Indicates.

Next, when the microprocessor is operating normally but the power is abnormally supplied, the high-speed watchdog signal F as shown in the section in FIG. 2C is supplied to the input terminal of the monostable multivibrator 31. At the same time as input to (B), it is input to the input terminal of the AND gate G32.

When the watchdog signal F in the high state is input to the input terminal B, the monostable multivibrator 31 receives the high signal in the clear terminal (/ CLR), and the input terminal (/ A). Since the low signal is being input, referring to the <function table> above, the low signal is output to the OR terminal (G31) through the output terminal (Q) and the high state is output to the inverted output terminal (/ Q). The signal is output to the AND gate G32. When the watchdog signal F in the high state is input, the OR gate G31 outputs the signal in the high state to the AND gate G33.

When the high state signal is inputted from the inverting output terminal (/ Q) of the monostable multivibrator 31 and the watchdog signal F in the high state is inputted, the AND gate G32 sends an AND gate to the high state output signal. Output to G33 and inverter G34.

When a high state signal is input from the OR gate G31 and the AND gate G32, the AND gate G33 outputs the high state signal to the base terminal of the transistor Q31.

When a high state signal is input to the AND gate G32, the inverter G34 outputs a low state signal to the AND gate G35. When the low state signal is input from the inverter G34, the AND gate G35 outputs the low state signal to the base terminal of the transistor Q32.

Accordingly, transistor Q31 is turned on and transistor Q32 is turned off.

Since the light emitting diode D31 emits light when the transistor Q31 is turned on, and the light emitting diode D32 does not emit light when the transistor Q32 is turned off, the microprocessor is operating normally, but power is abnormally supplied. Indicates.

As described above, in the embodiment of the present invention, it is possible to provide an error status display device of the watchdog circuit having an effect of clearly displaying the status of the error so that the user can easily recognize what kind of error has occurred. . This effect of the present invention can be used in the field of designing, manufacturing, and selling a display device of a watchdog circuit.

Claims (2)

When the watchdog signal F in the low state is input, the low signal is continuously output to the output terminal Q. When the watchdog signal F in the pulse state is input, the high signal is output to the output terminal Q. The monostable multivibrator 31 continuously outputs and the low state signal is continuously output to the output terminal when the watchdog signal F in the high state is input, and the output terminal Q of the monostable multivibrator 31. OR gate G31 for logically combining the signal inputted from the signal and the watchdog signal F and outputting the resultant signal, and the signal inputted from the inverted output terminal / Q of the monostable multivibrator 31 and the watchdog single. A first AND gate G32 for ANDing the arc F and outputting the resultant signal, and a second AND gate G33 for ANDing and outputting the signal input from the OR gate G31 and the first AND gate G32. And inverts the signal input from the first AND gate G32. Inverter G34 for outputting, a third AND gate G35 for performing an AND operation on the OR gate G31 and a signal input from the inverter G34, and the second and third AND gates G33, The first and second transistors Q31 and Q32, which are turned on and off by the signal input from G35, and the first and second transistors Q31 and Q32, respectively emit light as they are turned on and turned off, thereby causing an error. An error state display apparatus of a watchdog circuit, comprising first and second light emitting diodes (D31, D32) for indicating the state of?. 2. The error state display apparatus of a watchdog circuit according to claim 1, wherein said monostable multivibrator (31) is designed to have a pulse holding period longer than a period of a watchdog signal (F).