KR950007295A - Level conversion circuit of digital logic circuit - Google Patents

Level conversion circuit of digital logic circuit Download PDF

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Publication number
KR950007295A
KR950007295A KR1019930017118A KR930017118A KR950007295A KR 950007295 A KR950007295 A KR 950007295A KR 1019930017118 A KR1019930017118 A KR 1019930017118A KR 930017118 A KR930017118 A KR 930017118A KR 950007295 A KR950007295 A KR 950007295A
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KR
South Korea
Prior art keywords
digital logic
logic
level conversion
circuit
level
Prior art date
Application number
KR1019930017118A
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Korean (ko)
Inventor
노영섭
Original Assignee
이헌조
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이헌조, 주식회사 금성사 filed Critical 이헌조
Priority to KR1019930017118A priority Critical patent/KR950007295A/en
Publication of KR950007295A publication Critical patent/KR950007295A/en

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Abstract

본 발명은 서로 다른 레벨의 전원을 사용하는 디지털 로직 사이에서 로직 레벨을 변환시켜 주는 디지털 로직 회로의 레벨 변환회로에 관한 것으로서, 특히 +5V 전원을 사용하는 로직과 +3.3V 전원을 사용하는 로직 사이에 다이오드와 저항을 개입시켜 로직 레벨을 변환시켜 주는 디지털 로직 회로의 레벨 변환회로이다. 종래에는 제1도에서 보는 봐와같이, +5V 전원을 사용하는 디지털 로직부(1)와 +3.3V 전원을 사용하는 디지털 로직부(2)사이의 로직 레벨이 서로 다르기 때문에 이들을 직접 연결하게 되면 신호 전송을 오류 발생은 물론 과전압 및 과전류에 의한 소자 손상이 초래되는 문제점이 있고, 이를 극복하기 위하여 종래에는 레벨 변환을 위한 전용 IC(3)를 이용하여 +5V 디지털 로직부(1)와 +3.3V 디지털 로직부(2)사이의 신호 레벨 변환을 실현하게 되므로 레벨 변환 IC(3)에서의 과도한 전력소비의 문제점과, 전용 IC의 사용에 따른 가격 상승의 문제점이 있다. 본 발명은 로직 레벨을 변환하기 위한 전용의 IC를 사용하지 않고, +5V 로직을 +3.3V 로직으로 변환시키는 다이오드(D1)와, 부하저항(R1)을 이용해서 간소한 회로 구성으로 로직레벨의 변환을 실현하므로서 소비 전력을 줄이고, 로직 회로의 가격을 절감할 수 있도록 한 디지털 로직 회로의 레벨 변환회로이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit of a digital logic circuit that converts logic levels between digital logic using different levels of power supply. It is a level conversion circuit of a digital logic circuit that converts a logic level through a diode and a resistor. Conventionally, as shown in FIG. 1, since the logic levels are different between the digital logic unit 1 using + 5V power supply and the digital logic unit 2 using + 3.3V power supply, the signals are directly connected to each other. There is a problem that transmission is not only error occurs, but also device damage due to overvoltage and overcurrent, and to overcome this problem, a + 5V digital logic unit 1 and a + 3.3V are conventionally used by using a dedicated IC 3 for level conversion. Since signal level conversion between the digital logic units 2 is realized, there are problems of excessive power consumption in the level conversion IC 3 and a price increase due to the use of a dedicated IC. The present invention uses a diode (D1) for converting + 5V logic to + 3.3V logic and a load resistor (R1) without using a dedicated IC for converting the logic level. It is a level conversion circuit of a digital logic circuit that enables the conversion to reduce power consumption and reduce the cost of the logic circuit.

Description

디지털 로직 회로의 레벨 변환회로Level conversion circuit of digital logic circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 레벨 변환회로를 사용한 디지털 로직의 블록 구성도2 is a block diagram of digital logic using the level conversion circuit of the present invention.

제3도는 본 발명의 레벨 변환회로를 사용한 디지털 로직의 실시예 회로도3 is an exemplary circuit diagram of digital logic using the level conversion circuit of the present invention.

Claims (1)

+5V 디지털 로직부(1)에 캐소우드가 접속되고 애노우드는 3.3V 디지털 로직부(2)에 접속됨과 함께 저항(R1)을 통해 +3.3V 전원이 인가되는 다이오드(D1)와, 상기 다이오드(D1)의 애노우드에 +3.3V 전원을 공급하는 저항(R1)으로 구성된 디지털 로직 회로의 레벨 변환회로.A diode D1 to which a cathode is connected to the + 5V digital logic unit 1 and an anode is connected to the 3.3V digital logic unit 2 and + 3.3V power is applied through the resistor R1, and the diode Level conversion circuit of a digital logic circuit composed of a resistor (R1) for supplying + 3.3V power to the anode of (D1). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930017118A 1993-08-31 1993-08-31 Level conversion circuit of digital logic circuit KR950007295A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930017118A KR950007295A (en) 1993-08-31 1993-08-31 Level conversion circuit of digital logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930017118A KR950007295A (en) 1993-08-31 1993-08-31 Level conversion circuit of digital logic circuit

Publications (1)

Publication Number Publication Date
KR950007295A true KR950007295A (en) 1995-03-21

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930017118A KR950007295A (en) 1993-08-31 1993-08-31 Level conversion circuit of digital logic circuit

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KR (1) KR950007295A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100345006B1 (en) * 1999-11-19 2002-07-20 삼성전자 주식회사 dewy prevention apparatus of air conditioner and method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100345006B1 (en) * 1999-11-19 2002-07-20 삼성전자 주식회사 dewy prevention apparatus of air conditioner and method thereof

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