KR950007038A - Method of manufacturing thin film transistor electrode - Google Patents

Method of manufacturing thin film transistor electrode Download PDF

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Publication number
KR950007038A
KR950007038A KR1019930017315A KR930017315A KR950007038A KR 950007038 A KR950007038 A KR 950007038A KR 1019930017315 A KR1019930017315 A KR 1019930017315A KR 930017315 A KR930017315 A KR 930017315A KR 950007038 A KR950007038 A KR 950007038A
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KR
South Korea
Prior art keywords
thin film
film transistor
ito
electrode
manufacturing
Prior art date
Application number
KR1019930017315A
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Korean (ko)
Inventor
문규선
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019930017315A priority Critical patent/KR950007038A/en
Publication of KR950007038A publication Critical patent/KR950007038A/en

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Abstract

본 발명은 평판표시소자에 이용되는 액티브 매트릭스형 액정표시소자에 있어서 박막 트랜지스터 배열기판의 전극을 제조하는 방법에 관한 것으로, 좀 더 구체적으로는 소오스 및 드레인 구멍이 형성된 기판상에 ITO 및 AI층을 순차적으로 적층시키고, 패턴형성시에 상기 ITO 및 AI층을 AI 에칭용액으로 동시에 제거하는 박막 트랜지스터 전극의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing an electrode of a thin film transistor array substrate in an active matrix liquid crystal display device used in a flat panel display device, and more specifically, to the ITO and AI layers on a substrate on which source and drain holes are formed. The present invention relates to a method for manufacturing a thin film transistor electrode which is sequentially stacked and simultaneously removes the ITO and AI layers with an AI etching solution during pattern formation.

Description

박막 트랜지스터 전극의 제조방법Method of manufacturing thin film transistor electrode

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 방법에 따른 제조 공정도이다.2 is a manufacturing process diagram according to the method of the present invention.

Claims (2)

박막 트랜지스터 전극의 제조방법에 있어서, 소오스 및 드레인 구멍이 형성된 기판상에 ITO 및 AI 층을 순차적으로 적층시키고, 패턴형성시에 상기 ITO 및 AI 층을 AI 에칭용액으로 동시에 제거시키는 것을 특징으로 하는 박막 트랜지스터 전극의 제조방법.A method of manufacturing a thin film transistor electrode, wherein the ITO and AI layers are sequentially stacked on a substrate on which source and drain holes are formed, and the ITO and AI layers are simultaneously removed by AI etching solution during pattern formation. Method for manufacturing a transistor electrode. 제1항에 있어서, 상기 드레인전극은 ITO이고, 소오스전극은 ITO/AI적층 구조임을 특징으로 하는 박막 트랜지스터 전극의 제조방법.The method of claim 1, wherein the drain electrode is ITO and the source electrode has an ITO / AI stacked structure. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930017315A 1993-08-31 1993-08-31 Method of manufacturing thin film transistor electrode KR950007038A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930017315A KR950007038A (en) 1993-08-31 1993-08-31 Method of manufacturing thin film transistor electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930017315A KR950007038A (en) 1993-08-31 1993-08-31 Method of manufacturing thin film transistor electrode

Publications (1)

Publication Number Publication Date
KR950007038A true KR950007038A (en) 1995-03-21

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ID=66817878

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930017315A KR950007038A (en) 1993-08-31 1993-08-31 Method of manufacturing thin film transistor electrode

Country Status (1)

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KR (1) KR950007038A (en)

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