KR950006470B1 - Semiconductor memory device - Google Patents

Abstract

The semiconductor memory device is manufactured by using a charge coupled device. The manufacturing method has the steps of forming p-type substrate(32) on the semiconductor substrate(31), forming photodiode(33), thin film(36) and VCCD region(34) on the p-type substrate, forming trench(35) of oxide film, and forming a word line(37) straight across the diode, the region and the trench. The device has functions of read, write and save as a digital logic circuit does.

Description

Semiconductor memory device

1 is a structural cross-sectional view of a conventional CCD image device.

2 is a structural cross-sectional view of a conventional stack capacitor.

3 is a structural cross-sectional view of a conventional trench capacitor.

4 is a structural cross-sectional view of a memory device according to the present invention.

5 is one embodiment of FIG.

* Explanation of symbols for main parts of the drawings

31 substrate 32 p-type substrate

33: photodiode 34: VCCD area

35: oxide film 36: p ⁺ channel stop layer

37: wordline

The present invention relates to a memory device, and more particularly to a memory device using a CCD.

FIG. 1 is a structural cross-sectional view of a conventional CCD imaging device, in which a p-type well 2 is formed on an n-type substrate 1, and an n-type photodiode 3 and an n-type VCCD are formed at predetermined intervals on the p-type well 2. Forming a region 4 and forming a gate electrode 5 including the n-type photodiode 3 and the n-type VCCD region 4 transfer gate 5a, and forming the n-type VCCD region 4 and the photo. The p-type layer between the diodes 3 forms the channel stop layer 6 and the p-type thin line 7 is formed on the surface of the photodiode 3.

The operation of the CCD imaging device is as follows.

When light energy is incident on the n-type photodiode 3, the photodiode 3 converts the light energy into an image signal charge which is an electrical signal.

The image signal charge generated by the incident light energy is transferred to the VCCD region 4 by the high voltage applied to the transistor gate 5a.

The video signal charge moved to the VCCD area 4 is moved to the HCCD area (not shown) by the clock signal, and is moved to the output terminal in the HCCD area and output to the outside by the sensing amplifier.

Here, the p ⁺ type layer 7 on the photodiode 3 is for applying an initial virus. In addition, although the transfer gate 5a and the gate electrode 5 are all made of silicon, it was divided into the transfer gate 5a and the gate electrode 5 for convenience.

On the other hand, in the general memory device, as the capacity of the device increases, the density of the device increases and thus, the unit cell area decreases.

Accordingly, active research is being conducted in various fields such as developing a material of a good dielectric material to increase the capacitance in a small cell, finding a new manufacturing method that can increase the capacitor area, and reducing the thickness of the dielectric material.

2 is a structural cross-sectional view of a stack capacitor of a basic DRAM memory device, in which a gate oxide film 12, a gate 13, and a gate side wall oxide film 14 are formed in a predetermined portion on the semiconductor substrate 11, and the gate 13 is formed. Source and drain regions 15a and 15b are formed on a substrate by impurity ion implantation using a mask as a mask, an oxide film 6 is deposited on the entire surface, and a node polysilicon is formed on the source region 15b on which a contact window is formed. 17, a dielectric 18, and a plate polysilicon 19 are formed in this order to form a capacitor, and the bit line 10 is contacted on the drain region 15a.

As a result, a portion composed of the storage node polysilicon 17, the dielectric 18, and the plate polysilicon 19 serves as a capacitor, and the electrical signal accumulated in the capacitor is transferred to the bit line by the gate 13.

3 is a cross-sectional view illustrating a structure of a stack capacitor of a DRAM memory device according to another embodiment, in which a gate oxide film 28 and a gate 23 are sequentially formed on a predetermined portion of the semiconductor substrate 21, and the gate 23 and the gate oxide film 28 are formed. The source and drain regions 22 and 24 are formed on both surfaces of the semiconductor substrate 21 and the trenches are formed in the semiconductor substrate 21 on the other side of the drain region 24 with a predetermined depth. The oxide film 28, the node polysilicon film 25, the dielectric film 25, and the plate polysilicon 27 are sequentially formed.

Here, as described with reference to FIG. 2, the node polysilicon film 25, the dielectric film 26, and the plate polysilicon film 27 included in the trench structure may store electrical signals accumulated in the capacitor under the control of the gate 23. Transfer to the drain region 24 through the bit line.

However, the conventional DRAM memory device as shown in FIGS. 2 and 3 reduces the size of the memory cell in accordance with the shrinking trend of the current semiconductor device, but the reduction of the size of the memory cell has a limitation and also transfers a charge signal. Only the analog signal was processed, and digital signal processing was impossible.

The present invention aims to solve the above disadvantages, and to provide a memory device using a CCD image element having a memory cell function and having a larger area than that of a conventional transistor cell.

In order to achieve the above object, according to the present invention, in the CCD image element, the gate is extended in a straight line on the surface of the CCD image element so that the gate is a word line, the VCCD region is a bit line, and the photodiode and the VCCD region are separated outward. Form a trench structure for

Hereinafter, the configuration and operation of the present invention will be described in detail with reference to FIGS. 4 and 5.

4 is a cross-sectional view of a memory device according to an exemplary embodiment of the present invention, in which a p-type well 32 is formed on a substrate 31, and the n-type is disposed at a predetermined interval on the surface of the substrate 31 on which the p-type well 32 is formed. The photodiode 33 and the VCCD region 34 are formed repeatedly by impurity ion implantation, and isolation trenches are formed outside the photodiode 33 and the VCCD region 34. The photodiodes 33 and VCCD are formed. The word line 37 is formed in a straight line on the region 34 and the isolation trench.

Here, the isolation trench is filled with an oxide film to form the oxide film 35.

Here, the p ⁺ type thin film layer 36 is for forming a potential barrier of signal charges generated in the photodiode.

That is, the present invention is a structure of a memory device using a photodiode 33 as a capacitor and a VCCD region 34 as a bit line in a DRAM cell composed of one capacitor and one transistor.

Here, if the speed of the VCCD region 34 is slow, it can be inserted and replaced by metal or poly, and the concentration control by ion implantation of a predetermined portion of the photodiode 33 and the semiconductor substrate 31 is also performed. The threshold voltage is determined by.

In addition, when the device size is irrelevant, an ion implantation process of the photodiode 33 may be omitted or only a desired type of ions may be implanted to form memory devices having various modes.

5a to c are embodiments according to the present invention. First, the storage of data will be described with reference to FIG. 5a.

The photodiode 33 region is doped with n ⁺ and always accumulates electrons when the bias is zero, and when reading data, a p ⁺ doped channel is applied to the word line by applying a bias as shown in FIG. The potential of the stop area 37 is lowered and the potential of the area of the photodiode 33 storing data is increased so that the electrons of the photodiode move toward the VCCD area 34 through the transfer gate not shown in the figure.

The bias value at this time is a pinch-off value of the photodiode 33.

Also, when writing data, if the voltage of opposite polarity is applied to the word line, the potential of the VCCD region 34 where the data is located becomes high, and the potential of the photodiode 33 region becomes low, so that the transfer is not shown in the figure. The electrons are stored in the photodiode 33 toward the photodiode 33 toward the VCCD region 34 in the opposite direction as when read through the gate.

As described above, the semiconductor memory device of the present invention has a simpler structure than a process of a memory device using a general transistor, and can not only increase the area ratio of the conventional transistor, but also read, write, and store the same as a digital logic circuit. It enables the function of the memory device.

Claims (3)

A first conductive well is formed in a predetermined region of the semiconductor substrate, and an isolation trench is formed in an edge portion of the first conductive well, and a second conductive charge storage region, a thin film layer for a potential barrier, and a first barrier are formed therebetween. 2. A semiconductor memory device comprising: a two-conducting VCCD region formed horizontally side by side and a word line formed on a substrate to store charge in the charge storage region due to the bias of the word line. The semiconductor memory device according to claim 1, wherein the second conductive charge storage region is used as a capacitor. The semiconductor memory device according to claim 1, wherein the VCCD region is used as a bit line.