KR950005566B1 - Plazma display pannel & driving method - Google Patents

Abstract

The plasma display panel has front and rear plates(1a, 2a) separated to form a space filled with gas. A number of strip formed display electrodes (30a) are formed on one plate and scanning electrodes (10a) and common electrodes (30a) alternate on the lower plate. This has a dielectric layer (13a) under the electrodes and a further dielectric layer (14a) above. Connections (11a) are formed at the ends of the scanning electrodes. The second connection (12a) is formed as a strip. The extension of the dielectric material (131a) between the contacts provides a capacitor function.

Description

Plasma Display Panel and Driving Method thereof

1 is an equivalent circuit diagram of a plasma display panel according to the present invention.

2 is a partial perspective view of a first embodiment of a plasma display panel according to the present invention;

3 is a cross-sectional view taken along the line III-III of FIG.

4 is a cross-sectional view taken along the line IV-IV of FIG.

5 is a partial perspective view of a second embodiment of the plasma display panel according to the present invention;

6 is a cross-sectional view taken along the line VI-VI of FIG.

7 is a view corresponding to FIG. 6 and shows another modified example of the present invention.

FIG. 8 is a partial cross-sectional view of a third embodiment of a plasma display panel according to the present invention corresponding to FIG.

9 is a drive waveform diagram in an embodiment of a method of driving a plasma display panel according to the present invention;

10 is a drive waveform diagram in an embodiment of a method of driving a plasma display panel according to the present invention.

* Explanation of symbols for main parts of the drawings

10, 10a, 10b: scan electrode 20, 20a, 20b: common electrode

30, 30a, 30b: display electrodes 1, 1a, 1b: front panel

2, 2a, 2b: back plate

The present invention relates to a plasma display panel, and to a structure and a driving method of an AC-DC hybrid memory type plasma display panel.

In general, it is well known that a plasma display panel is classified into an AC type and a DC type based on the discharge method. In the AC plasma display panel, the discharge is generated by the AC driving voltage through the right dielectric layer, and the DC plasma display panel is caused by the DC driving voltage supplied when the two opposing electrodes are directly exposed to the discharge space.

Such plasma display panels are subdivided into various types according to their accompanying structure. Recently, a plasma display panel has been proposed to improve low luminance, which is a disadvantage of the plasma display panel, and to improve responsiveness. Representative examples are "DC type pulse memory plasma display panel" (see Japanese Laid-Open Patent Publication No. 64-211831) of NHK Broadcasting Technology Research Institute of Japan, and "trigger discharge type plasma display panel" (see US Patent 4,562,434) of Sony Corporation, Japan. The NHK plasma display panel applies a memory discharge effect so that the visible luminance is improved through a longer discharge, and after the discharge is transferred to another discharge line, the preceding discharges of the previous lines are at most 1 frame ( Discharging can be continued for one complete screen). The plasma display panel of NHK Broadcasting Technology Research Institute uses a "space charge" inside the panel as its memory means, but the memory discharge is sustained by applying a discharge sustain pulse lower than the discharge start voltage and higher than the discharge sustain voltage from the outside. Adopted. However, it is practically very difficult to apply high-frequency discharge sustain pulses to both electrodes in the plasma display panel, and in many cases, abnormal operation occurs during operation. It is also not easy to use space charge as a memory means. In addition, the Sony plasma display panel is irrelevant in memory and is intended to improve the responsiveness by shortening the discharge start time after applying a signal. The wall charge acts on the voltage as the rising voltage to the applied voltage, so that the display discharge can be generated quickly.

In the conventional plasma display panel described above, the NHK plasma display is DC type, and thus, the material of the negative electrode exposed to the discharge space and impacted by the discharge ions must be improved to apply an extension of its life through suppression of negative electrode damage. Recently, a material having a thermal shock resistance such as LaB ₆ has been used, but a satisfactory result has not been obtained, and there is still a problem for extending its life. In addition, since it is a DC type, it does not have a memory in principle and thus does not obtain desired brightness under the so-called line scanning driving method.

As a solution to this problem, the memory is eventually implemented in a circuit. As a result, the discharge frequency is increased as compared with the linear sequential driving method, which is also disadvantageous in terms of its lifetime. Moreover, when applied to the color type, the mass of the discharge gas is heavier than the gas in the monochromatic type and the discharge voltage is high.

In the case of Sony's plasma display panel, the trigger discharge is used, but the response is excellent, but since the memory function is not actually provided, there is a disadvantage in terms of its brightness compared to other plasma display panels.

In addition, another example of a known AC plasma display panel may be exemplified by U.S. Patent 4,044,349 of Fujitsu limted. It has a structure in which a cathode and an anode of a simple X-Y matrix type are arranged on the front plate and the back plate, and the discharge electrode group for the address and the discharge electrode group for maintaining the discharge overlap each other. All of these plasma display panels are driven by an alternating current type, so that the driving circuits are complicated.

Meanwhile, Thomson, France, proposed a plasma display panel having a new structure through European Patent Publication No. 0 357 485 A1.

The plasma display panel has a structure in which the Y electrode to which the sustain voltage and the scan voltage are applied and the E electrode to which the maintenance voltage is applied are orthogonal to the data electrode (or the X electrode), so that the cost of the driver of the Y electrode is high. As a result, the tutor of light emission is long in a memory system by AC discharge, and the driver can be easily destroyed by accumulated high heat.

An object of the present invention is to provide an AC-DC complex memory plasma display panel whose structure is improved to selectively provide only the advantages of the conventional DC plasma display panel and the AC plasma display panel.

Another object of the present invention is to provide a memory type plasma display panel having a simple structure and stable discharge and improved durability.

It is yet another object of the present invention to provide a memory type plasma display panel suitable for color image display.

In order to achieve the above object, the plasma display panel of the present invention comprises: an opposing front plate and a back plate which are spaced apart from each other at a predetermined interval to form a gas space therebetween; A plurality of parallel electrodes in a first direction formed on an inner surface of the front plate; Disposed on the rear plate in a second direction orthogonal to the first direction, and protected by a dielectric layer coated thereon, thereby not being in contact with the gas in the discharge space, and electrically connected to one end thereof. A plurality of stripe-shaped scan electrodes having a first terminal and a second terminal indirectly connected to the capacitor layer by a dielectric material; A common electrode provided on the back plate together with the first electrode and having a directional coupling through a dielectric layer; A plurality of barrier ribs disposed in parallel with the first electrode between the front plate and the rear plate; Its features are that it has a.

In the present invention as described above, the common electrode is formed as a single layer at the bottom of the scan electrode as a specific type, and a dielectric layer is provided therebetween to form a sandwich structure with them.

Another type of common electrode is formed by separating a plurality of stripe elements that are electrically common. At this time, the divided elements of the common electrode may be provided by interposing a dielectric layer on the bottom of the scan electrode as in the above type.

On the one hand, each element to be indispensable of the common electrode is arranged side by side and alternately on the same plane as the scan electrode, and is arranged side by side and alternately on these planes, and the elements of these scan electrode and the common electrode The dielectric layer is provided on the field to form one AC discharge structure.

In the above types, the scan electrode and the common electrode are mutually positioned to enable discharge through the discharge space.

On the other hand, in the driving method of the plasma display panel, the driving method of the present invention comprises: 1. For standby of memory discharge, the second terminal and the common electrode of every scan electrode each have a periodic voltage of 0 volt and a discharge sustain potential, respectively. First and second memory signals having first and second memory pulse components are respectively applied, and pulses of the first and second memory signals are alternately applied to the second terminal and the common electrode of the scan electrode at predetermined intervals. A discharge sustain voltage difference for memory discharge is maintained between the scan electrode and the common electrode, and 2. at the display terminal and the second terminal of the scan electrode which are orthogonal thereto while maintaining a predetermined distance from the scan electrode to start discharge, While the potential difference between the first and second addressing signals of the first and second memory signals is 0 volts, the first and second addressing signals are discharged. A predetermined voltage having a bias voltage of another potential having a potential difference of less than or equal to a voltage, the relative potential difference of those voltages having a potential difference of at least a discharge initiation voltage, and each having a potential difference of less than or equal to the first and second memory pulses and a discharge sustaining voltage; Has a first and second write pulses of a period, and 3. at a time when a second memory pulse is applied to the common electrode to terminate the discharge, the second memory pulse and the potential difference are made through the second terminal of the scan electrode. The characteristic is that a pulse having a value equal to or higher than the discharge start voltage is applied.

According to another driving method of the present invention, the first memory signal and the second memory signal are applied to the second terminal and the common electrode of all scan electrodes for standby of memory discharge. The first memory signal has an bias potential of 0 volts as an alternating square wave, and has a positive memory pulse component and a negative memory pulse component on a coin, and the second memory signal is the first memory. By having an anti-phase with a signal, the relative potential difference between the scan electrode and the common electrode maintains a value at which discharge can be maintained smaller than a discharge start voltage, and maintains a potential difference. The first and second addressing signals are disposed on the display electrode and the first terminal of the scan electrode which are perpendicular to the display electrode while being kept at a predetermined distance from the electrode. The potential wave between the first and second memory signals is applied at a time of 0 volts, and the first and second addressing signals have a potential difference equal to or lower than a discharge sustain voltage that is constantly applied to the first terminal of the scan electrode and the display electrode. The bias voltages having different potentials; And first and second write pulses such that their relative potential differences have a value equal to or greater than the discharge start voltage, and each of them has a potential difference less than or equal to the first and second memory pulses and a discharge sustain voltage; And 3. When the first and second memory pulses are applied to the second electrode and the common electrode of the scan electrode to terminate the discharge, the second memory pulse and the second memory pulse are connected through the first terminal of the scan electrode. The characteristic feature is that a pulsed erase signal having a potential difference equal to or greater than the discharge start voltage is applied.

In the driving method of the present invention as described above, the bias voltages of the first and first memory pulses applied to the common electrode and the second electrode of the scan electrode are the same, and the erase signal is applied to the first electrode of the scan electrode. The bias voltage of is equal to the bias voltage of the write signal.

In particular, the bias voltage of the first write signal maintains a lower potential than the second write signal, and preferably, the first write signal is positive and the second write signal is negative.

1 is an equivalent circuit diagram of a visible plasma display panel showing the concept of the present invention.

A pair of memory electrodes including the scan electrode 10 and the common electrode 20 in the horizontal direction are provided in parallel with each other. Each end of the scan electrode 10 is provided with a first terminal 11 and a second terminal 12. The first terminal 11 is connected to the scan drive (×) and is directly connected to the scan electrode 10, and the second terminal is indirectly connected to the capacitor 13. The common electrodes are connected in common and always maintain mutual equipotential. Reverse-phase AC square waves are respectively applied to the second terminal 12 and the common electrode 20 of the scan electrode 10, and their relative potential periodically maintains a discharge sustain voltage below the discharge start voltage. Here, the discharge sustaining voltage is a potential that is enough to sustain the discharge that has already started, and is lower than the discharge starting voltage. The first terminal of the scan electrode 10 and the display electrode 30 are applied from the data drive Y with a write pulse whose discharge potential has a discharge start voltage. The write pulse is applied when the upper potential difference of each discharge sustain signal applied to the second terminal 12 of the scan electrode and the common electrode 20 is 0 volts, and the potential difference between these discharge sustain signals is discharged. It must be less than the starting voltage.

Embodiments of the present invention will now be described in detail.

Example 1

2 and 3a and 3b, the front plate 1a and the back plate 2a are separated from each other at predetermined intervals to form a gas space in which discharge gas is filled therebetween. On the inner surface of the front plate 1a, a plurality of spherical display electrodes 30a are provided side by side in the first direction. In addition, a scan electrode 10a and a common electrode 20a are alternately formed on the front plate 2a, and a first terminal 11a is provided at an end of the scan electrode 10a, and a second terminal under the scan electrode 10a. The dielectric layer 3a is provided with the dielectric layer 3a interposed therebetween. The second terminal 12a is formed of a single body extending in the direction in which the first terminal 11a is arranged. Therefore, each scan electrode may be separated into corresponding independent shapes. In addition, the dielectric layer 3a and the dielectric layer 3a are formed on the surface of the back plate 2a, and a tip end thereof is provided between the first terminal 11a and the second terminal 12a so that the first terminal 11a is provided. ) And the second terminal 12a serve as a capacitor layer 131a. In this case, the second terminal 12a may be close to the scan electrode 10a so as not to overlap the common electrode 20a. In the above structure, the overlapping area between the second terminal 12a and the first terminal 11a and / or the scan electrode 10a and the distance therebetween change the capacitance of the capacitor 131a. Therefore, the required overlap area and the thickness of the dielectric layer 13a should be adjusted according to the design conditions. On the other hand, the terminal of the common electrode 30a is provided in the opposite direction to the first terminal 11a, and is electrically connected in common. An upper dielectric layer 14a is formed on the surface of the scan electrode 11a and the common electrode 20a and the surface of the dielectric layer 13a exposed between the upper electrode layer 14a and the upper surface of the scan electrode 11a and the common electrode 20a. It is isolated from the gas space.

Second Embodiment

5 and 6, the front plate 1b and the back plate 2b are separated from each other at predetermined intervals to form a gas space in which discharge gas is filled therebetween. An upper insulating layer 14b is formed on the upper surface layer of the front plate 1b, and a lower dielectric layer 13a is formed thereunder. Between the lower dielectric layer 13a and the back plate 2b, the common electrode 20b positioned at the bottom of the scan electrode 10b and the bottom of the first terminal 11b of the scan electrode 106 are positioned. The second terminal 12b is provided. The second terminal 12b is formed of one body extending in the direction in which the first terminal 11 is arranged, and may be separated into a plurality of independent elements corresponding to each scan electrode, if necessary.

In addition, the dielectric layer 3 is formed on the surface of the back plate 2, and a tip end thereof is provided between the first terminal 11 and the second terminal 12 so that the first terminal 11 and the first terminal 11 are formed. It serves as a capacitor layer between the two terminals 12. In this case, the second terminal 12 may be close to the scan electrode 10 such that the second terminal 12 does not overlap the common electrode 20. In the above structure, the overlapping area between the second terminal 12 and the first terminal 11 and / or the scan electrode 10 and the spacing therebetween change the capacitance of the capacitor, so that the necessary overlap is required. The area and thickness of the dielectric layer should be adjusted according to the design conditions. On the other hand, the terminal (not shown) of the common electrode 20b is provided in the opposite direction to the first terminal 11b, and the whole is electrically connected in common.

The second embodiment of this structure is characterized in that the stripe-shaped common electrode 20b is located on a different plane from the scan electrode 10b. In some cases, as shown in FIG. 10b and the common electrode 20b may be positioned to be offset from each other, and the whole may be electrically connected in common while the common electrode 20b is disposed in a direction orthogonal to the scan electrode 10b. It is substantially the same as the case where it is functionally arranged in the same direction as the scan electrode 10b.

As such, when the common electrode 20b is formed on a plane different from the scan electrode 10b, the arrangement interval of the scan electrode 10b can be significantly narrowed, so that a high density image can be formed in comparison with the first embodiment.

Third Embodiment

This embodiment has a structure similar to that of the second embodiment as a whole, and there is a difference in that the common electrode 20c is formed of the surface single layer of the back plate 2c as shown in FIG. 7 only.

Hereinafter, the driving method of the present invention for driving the plasma display panel having the above structure will be described through two embodiments.

The driving method of the present invention is divided into three steps.

The first stage is a pre-discharge stage, which is a standby driving stage that allows the discharge to continue for a predetermined period of time once the discharge is induced. The second stage is an ignition stage causing discharge in the discharge space in the standby driving stage. It is a step of terminating discharge which continues after a predetermined period of time.

In the standby step, a pulsed memory signal is applied between the scan electrode and the common electrode to maintain the electric potential between the two electrodes, and at this time, the two electrodes alternately act as the cathode and the anode. In the ignition step, a write pulse of a discharge start voltage is applied to the scan electrode and the data electrode, and a discharge start voltage pulse is applied to the data electrode and the scan electrode for a very short time.

[Example 1 of Driving Method]

A first embodiment of a driving method will be described with reference to FIG.

In the standby state of the memory discharge, the first and second memory pulse components for each period T having zero bias voltage and discharge sustain potential Vs at the second terminal and the common electrode of all the scan electrodes, respectively. Pulses A1 and B1 of the first and second memory signals, respectively, are applied. Therefore, the pulses A11 and B11 of the first and second memory signals having a bias potential of zero volt are alternately applied to the second terminal and the common electrode of the scan electrode at intervals of half a period T / 2. The scan electrode and the common electrode alternately have a role of a cathode and an anode at half-cycle intervals. In addition, a discharge holding voltage difference for memory discharge is maintained between the scan electrode 10 and the common electrode 20 during the period t of applying the memory pulse.

In order to start discharging, the display electrodes orthogonal to the scan electrodes and the second terminals of the scan electrodes while maintaining the predetermined distances of the scan electrodes are provided with the first and second memory signals (D1). It is applied when the potential difference between A1) and (B1) is zero volts. Therefore, the discharge is started between the display electrode and the scan electrode by the addressing signals C1 and D1. At this time, the discharge is soon extinguished because wall charges are accumulated in the dielectric layers 14a and 14b covering the scan electrode 10, and priming particles are suspended in the space. The wall charge is combined with the dielectric voltage of the next cycle to increase the level of the effective voltage applied to the discharge cell, so that the discharge can be started or continued even by a potential difference below the discharge start voltage. That is, in the state where the wall charge is generated, periodic memory pulses of the first and second memory signals having a potential lower than the initial discharge start voltage are applied to the scan electrode and the common electrode, and the discharge continues by the wall charge.

The first and second addressing signals C1 and D1 have bias voltages Vs / 4 (−Vs / 4) of different potentials, and the bias voltages are relative to the discharge sustain voltage Vs or less. Has a potential difference. Therefore, when the bias voltage of the addressing signal is applied, the discharge does not start because the potential difference between all the positive electrodes has a value equal to or lower than the discharge start voltage Vf. In this state, the first and second write pulses C11 and D11 having the state potential difference of the voltages having the potential difference of the discharge start voltage Vf are the first terminal of the scan electrode 10 and the display electrode. The addressing discharge starts as a ratio by being applied to 30 for a predetermined time Tw. At this time, since the first and second write pulses C11 and D11 have a potential difference less than or equal to the discharge sustain voltage from the first and second memory pulses A11 and B11, the display electrode 10 is displayed with the display electrode 10. It is caused only between the electrodes 30.

On the other hand, if the erase pulse is applied at any point during the memory discharge as described above, the wall charge disappears and the discharge is stopped. The discharge termination is performed to suppress the generation of wall charges that sustain the memory discharge below the discharge start voltage. The suppression of the generation of wall charges is made possible by causing a strong discharge for a very short time without giving time for wall charges to form.

Therefore, in order to end the memory discharge, when the second memory pulse B11 is applied to the common electrode, the second terminal 12 of the scan electrode 10 is relative to the second memory pulse B11. The generation of the wall charge is suppressed by applying an erase pulse D12 having a potential difference of a value of the discharge start voltage for a predetermined time (Tw / 10-Tw / 5) shortly.

[Example 2 of Driving Method]

In order for the memory discharge to be standby, the first memory signal A2 and the second memory signal B2 are applied to the second terminal and the common electrode of all the scan electrodes. The first memory signal has a bias potential of 0 volts as an alternating square wave, and thus has a positive memory pulse component A21 and a negative memory pulse component A22 having a potential of Vs / 2 alc-Vs / 2. ) And the second memory signal B2 having the positive memory pulse component B21 and the positive memory pulse component b22 has a phase difference of 180 ° with respect to the first memory signal A2, that is, an inverse of the first memory signal. It has an anti phase. Therefore, the relative potential difference between the scan electrode 10 and the common electrode 20 is lower than the inversion start voltage V5 based on the first and second memory signals.

In order to start discharging, the display electrode 30 and the first terminal 11 of the scan electrode 10 orthogonal to the display electrode 30 while maintaining a predetermined distance from the scan electrode 10 are provided with first and second addressing signals C2, (D2) is applied when the potential difference between the first and second memory signals A2 and B2 is zero volts. The first and second addressing signals C2 and D2 may have a potential difference less than or equal to a discharge sustain voltage Vs applied to the first terminal 11 of the scan electrode 10 and the display electrode 30. Have a bias voltage (3Vs / 4) (-Vs / 4) of mutually different potentials, and at the same time, their relative potential difference has a value greater than or equal to the discharge start voltage and each of the first and second memory pulses The first and second write pulses C21 and D21 which have a relative potential difference below (A21) and (B21) and the discharge sustain voltage are applied.

In order to finish discharging, the scan is performed when the first and second memory pulses A21 and B21 are applied to the second electrode 12 and the common electrode 20 of the scan electrode 10. Through the first terminal 11 of the electrode 10, a pulsed erasing pulse D22 having a potential difference greater than or equal to the discharge start voltage is applied to the second memory pulse B21 for a short time Tw to generate white charge. The memory discharge is terminated by suppressing this.

In the driving method of the present invention as described above, the bias voltages of the first and second memory pulses applied to the second electrode and the common electrode of the scan electrode are the same, and the erase signal is applied to the first electrode of the scan electrode. The bias voltage of is equal to the bias voltage of the write signal. In particular, the bias voltage of the first write signal maintains a lower potential than the second write signal, the first write signal is a positive potential, and the second write signal is a negative potential.

The plasma display panel of the present invention described above has an alternating current type memory discharge structure in which the scan electrode and the common electrode which are discharged for a long time and the common electrode are stably protected by the dielectric layer. Since there is no difficulty and the addressing discharge is substantially a direct current discharge method, the circuit configuration of the addressing part is easy, and the discharge for addressing occurs quickly without being delayed as in the AC discharge method. That is, the present invention has an AC-DC composite discharge structure with the advantages of a direct-current plasma display panel and an alternating-current plasma display panel. In addition, since the AC type stable memory discharge is possible at the time of discharge, it has high responsiveness due to the stable discharge compared to the conventional plasma display panel, and its lifetime is also long. The present invention is more suitable for displaying a color image than a mono chrome type, and is not limited by the embodiments exemplified in the future, and various modifications may be made based on the embodiments.

Claims (14)

Mutually opposing front and back plates which are spaced apart from each other at a predetermined interval to form a gas space therebetween; A plurality of parallel display electrodes in a first direction formed on an inner surface of the front plate; Disposed on the rear plate in a second direction orthogonal to the first direction, and protected by a dielectric layer coated thereon, thereby not being in contact with the gas in the discharge space, and electrically connected to one end thereof. A plurality of stripe-shaped scanning electrodes having a first terminal 11 and a second terminal indirectly connected to the capacitor layer by a dielectric material; A common electrode provided on the back plate including the first electrode and having a capacitive coupling through a dielectric layer; A plurality of barrier ribs disposed in parallel with the first electrode between the front plate and the rear plate; Plasma display panel comprising a. The plasma display panel of claim 1, wherein the common electrode is formed as a single layer on the bottom of the scan electrode, and a dielectric layer is provided therebetween to form a sandwich structure therewith. The plasma display as claimed in claim 1, wherein the common electrode is separated into a plurality of stripe elements electrically connected to each other, and the divided common electrode elements are provided on the bottom of the scan electrode via a dielectric layer. panel. 4. An element discharge according to claim 3, wherein each element to be divided of the common electrode is arranged side by side and alternately on the same plane as the scan electrode, and the dielectric layer is provided on the elements of the scan electrode and the common electrode. A plasma display panel comprising a structure. The plasma display panel of claim 1, wherein the common electrode is provided at a bottom of the scan electrode with an insulating layer interposed therebetween. The plasma display panel of claim 5, wherein the common electrode is formed of a single layer. The plasma display panel of claim 5, wherein the stripe-like elements in which the common electrode is separated into the stripe-like elements side by side are electrically connected in common. 8. The plasma display panel of claim 7, wherein the common electrode has a stripe element arranged in a direction parallel to the scan electrode. 10. The plasma display panel of claim 8, wherein each stripe element of the common electrode is provided to be eccentric with the scan electrodes. 8. The plasma display panel of claim 7, wherein the stripe elements of the common electrode are arranged in a direction orthogonal to the scan electrodes. The plasma display panel according to any one of claims 1 to 10, wherein the first terminal and the second terminal are provided to face each other with a dielectric layer interposed therebetween, so that the capacitor is configured. 12. The plasma display panel of claim 11, wherein the second terminal comprises a single body arranged in an arrangement direction of the first terminal. In the method of driving a plasma display panel, a) for standby of memory discharge, periodic first and second memory pulses having a bias voltage of 0 volt and a discharge sustain potential at the second terminal and the common electrode of all scan electrodes, respectively; The first and second memory signals each having a component are applied to each other, and pulses of the first and second memory signals are alternately applied to the second terminal and the common electrode of the scan electrode. A discharge sustain voltage difference for memory discharge is maintained between the first and second addressing signals at the display electrode and the second terminal of the scan electrode which are orthogonal to the scan electrode while maintaining a predetermined distance to start discharge. The potential difference between the first and second memory signals is applied at a time of 0 volts, but the first and second addressing signals have a potential difference less than or equal to the discharge sustain voltage. Having a bias voltage of a different potential, the relative potential difference of these voltages having a potential difference equal to or greater than the discharge start voltage, and each of which has a potential difference equal to or less than the first and second memory pulses and the discharge sustain voltage; 2) a write pulse; and c) at a time when a second memory pulse is applied to the common electrode to terminate the discharge, the second memory pulse and the potential difference are greater than or equal to the discharge start voltage through the second terminal of the scan electrode. A method of driving the plasma display panel according to claim 1, wherein a pulse is applied. In the method of driving a plasma display panel, a) a first memory signal and a second memory signal are applied to the second terminal and the common electrode of all the scan electrodes in order to standby the memory discharge. As a square wave, it has a bias potential of 0 volts, and has a positive memory pulse component and a negative mori pulse component on a coin, and the second memory signal has an antiphase with the first memory signal, thereby providing the scan electrode and the common electrode. Maintains a value at which the relative potential difference between the discharge potential is smaller than the discharge start voltage and maintains the potential difference; The first terminal is input when the potential difference between the first and second addressing signals is 0 volts. Doedoe, the first and second addressing signals are bias voltages of mutually different potentials having a potential difference between the discharge sustain voltage is applied at all times less than the first terminal and the display electrode of the scan electrode; And the relative potential difference has a value equal to or greater than the discharge start voltage, each of which has a first and second write pulse such that the first and second memory pulses have a potential difference less than or equal to the discharge sustain voltage. At the time when the first and second memory pulses are applied to the second electrode and the common electrode of the scan electrode to terminate the discharge, the second memory pulse and the potential difference are greater than or equal to the discharge start voltage through the first terminal of the scan electrode. A method of driving a plasma display panel according to claim 1, wherein a pulsed erase signal having a value is applied.