KR950005142B1 - Clock synchronization control method of distributed node switching system - Google Patents

Abstract

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Description

Clock Synchronization Control Method in Distributed Node Switching System

1 is a system-wide block diagram to which the present invention is applied.

2 is a block diagram of a clock synchronization related module according to the present invention.

3 is a memory configuration diagram according to the present invention.

4 is a system process flow diagram according to the present invention, which is a process flow diagram at boot time.

5 and 4 are flowcharts illustrating clock part clock error processing during system operation according to the present invention.

The present invention relates to a clock synchronization control method of a switching system, and more particularly, to a control method of clock synchronization of a distributed node switching system composed of a plurality of nodes.

A distributed multi-node switching system refers to a multi-node distributed node exchange system in which one private exchange that can be operated independently is a node, and constitutes a network with multiple nodes. .

In the conventional clock synchronization method, clock synchronization is specified in hardware at the time of distributed node switching or system configuration. In addition, in order to ensure the reliability of clock synchronization, a back-up synchronous clock source is set (configured) in hardware to prepare for an error of the originally specified clock synchronization.

As described above, the conventional distributed node switching system which operates by designating clock synchronization in advance in hardware is operated to synchronize the synchronization clock source when the system is driven by a predetermined synchronization clock source. In addition, in order to improve reliability, when an error occurs in the originally designated synchronous clock source, the system is operated to synchronize the system as a back-up synchronous source designated by hardware, thereby performing clock synchronization.

However, the conventional clock synchronization method as described above is difficult to cope with more flexibility in the operation of the system by taking the clock synchronization between nodes depending on the system hardware configuration. That is, when connected to an external communication network, the clock synchronization of each node cannot be easily controlled. If the clock synchronization of each node cannot be easily controlled as described above, when an abnormality occurs in the clock source, it is difficult to perform a normal service by easily northing.

Accordingly, an object of the present invention is to provide a clock synchronization control method for smooth communication between nodes in an exchange system composed of multiple nodes.

Another object of the present invention is a clock synchronization control method for facilitating communication for communication between nodes in a switching system composed of multiple nodes and enabling communication by controlling clock synchronization of each node even when connected to an external network. In providing.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 5.

1 is a block diagram of an entire distributed node system to which the present invention is applied, and this configuration is as follows.

A control unit 10 for controlling the entire system, a clock unit 11 for supplying a clock required for the system or selecting an external clock inputted from the outside under the control of the control unit 10 and providing the system to the system, program data and The memory unit 12 storing the related data and accessing the stored data under the control of the control unit 10, and the switch unit 13 which is switched under the control of the control unit 10 and connects each subscriber. And an inter-node interface (INI) 15 for interfacing data and clocks between nodes, and a clock inputted from the node-connector 15 to check events of the subscribers, And a hard disk 16 that stores programs and data of the system.

2 is a block diagram of a clock synchronization-related module according to the present invention, which shows a connection configuration of the clock synchronization-related module shown in FIG. As a module in charge of interface between each node (interface) or interface with external digital trunk, it measures various performance parameters through line monitoring and checks whether the 8KHz synchronous source (S8K) extracted from the line is valid and then clocks it. 11) a node connector 145 having a function of transmitting to a module, and a module that manages one subscriber shelf, and collects 8 kHz synchronization signals 8 transmitted from one or more node connectors. Subscribers 14a and 14b including a selector which transmits to the clock unit 11 and selects one of clocks supplied from a node connecting unit in response to the control of the controller 10, and the controller 10 of the controller 10. A clock unit 11 which selects a clock supplied to the system by control and extracts a required clock; and a synchronous clock as specified in the system or according to the state of the system clock. It consists of the control unit 10 to control the selection.

The configuration of FIG. 2 shows an example in which the first subscriber 14a in the subscriber 14 selects the 8khz synchronization signal from the node connector 15 and provides it to the clock 11.

3 is a memory diagram according to the present invention, which is located in the hard disk 16 and the memory unit 12 shown in FIG. 1, and stored in the memory unit 12 under the control of the controller 10. The data is changed.

SYNC_SEL_DB shown in FIG. 3A stores eight types of system node synchronization information for each priority, that is, master / slave information for the current node and synchronization clock source node connection information. F_MS, F_PRMLNK, and F_SNDLNKs in FIG. 3A are the following information, respectively.

F_MS (FLAG-MASTER-SLAVE): It indicates whether a node is a master or a slave. It has a size of 1 byte, and when the least significant bit is "1", it means a master node and when it is "0", it means a slave node. do.

F_PRMLNK (FLAG-PRIMARY INI LINK): Indicates a link of a first node connection that supplies a clock synchronization source, and has a size of 1 byte.

F_SNDLNK (FLAG-SECONDARY INI LINK): Indicates a link of a second node connection that supplies a clock synchronization source, and has a size of 1 byte.

SYNC_SEL_WA shown in FIG. 3B stores the state of the clock synchronization source of the first node connection link and the clock synchronization source of the second node connection link, which are the node synchronization clock source node connections in SYNC_SEL_DB of FIG. 3A. Area.

In the SYNC_SEL_WA, the F_PRMSTS (FLAG-PRIMARY-STATUS) storing the data representing the source state of the synchronous clock stored in the link of the first node (PRIMARY INI LINK) stored in the F_PPRMLNK of the SYNC_SEL_DB and the second node connected to the F_SNDLINK There is an F-SNDSTS (FLAG-SECONDARY-STATUS) that stores data representing the synchronous clock source state. Each of the F_PRMSTS and F_SNDSTS indicates the state of each synchronous clock source as 1 byte data as shown in FIG. 3C as follows.

In addition, the F-SYNC-PTR (FLAG-SYNC-POINTER) shown in FIG. 3D is an area in which a value indicating the currently selected SYNC-SEL-DB is stored.

4 is a flowchart illustrating a system process during system boot according to the present invention, and FIG. 5 is a control flowchart for executing clock error processing of a clock unit during system operation according to the present invention.

Hereinafter, the operation of the clock synchronization control according to the present invention will be described in detail with reference to the configuration of FIGS. 1 and 2, the memory map shown in FIG. 3, and the flowcharts of FIG. 4 and FIG. The implementation method according to the present invention is divided into a processing part during system operation and a processing part during system operation. First, the processing operation during system operation is described in detail with reference to FIGS. 1, 2, 3, and 4. Explain.

In order to operate the distributed node switching system as shown in FIG. 1, each of the nodes Node0 to Node7 is configured to boot programs and data necessary for system operation from the hard disk 16 in the node NODEO. have. Therefore, in the case of a node without a hard disk in the system, since the program and data of its own node are booted from other nodes, communication between nodes is required and the synchronization between nodes is required even during system booting. The resulting process flow is as shown in FIG.

When the operation of the system is started, the controller 10 first searches for the presence of the hard disk 16 in step (4a) of FIG. 4 to search whether its own node can boot independently. If the search result is bootable, the controller 10 controls the clock unit 11 in step 4B of FIG. 4 to select a clock generated by itself as a synchronous clock. The controller 100 accesses and boots the program and data of its own node from the hard disk 16 in step 4c.

When the booting is completed by such an operation, the control unit 10 shown in FIG. 1 accesses clock synchronization-related data among the data accessed from the hard disk 16 in step 4d, and the clock is cleared by the accessed data. The clock synchronization source of the unit 11 is reselected. That is, in step 4c, the control unit 10 selects the synchronization source of the clock unit 11 by referring to the F_MS field in SYNC_SEL_DB and the data of the F-SNDLINK as shown in FIG. For example, if it is its own master node, it selects its own clock in the clock section 11 as a synchronous source clock, and if it is a slave, it is the other node of the link corresponding to the value of F-PRMLNK or F-SNDLINK. The clock supplied from the connection node unit 15 is selected as the synchronization source. At this time, the connection node unit 15 checks whether the state of the clock synchronization source input from the other node is valid and transmits the state to the clock unit 11.

If it is determined that self booting is not possible in step 4a (4a), the control unit 10 receives other information through the node connection unit 15 detected by data transmission / reception with the subscriber unit 14 in step (4e). Receive boot-related data from the node. In this case, the clock source transmitted from the node connector 15 of the node connected to the first node is selected. The controller 10 selecting the clock source as described above transmits a boot request message for booting to another node supplying the clock source through the node connection unit 15 in step 4f. The controller 10 checks whether a boot is possible by analyzing a response message transmitted from another node in response to the transmitted boot request message in step 4g. If it is determined that the node supplying the clock source is bootable in FIG. 4 (4g), the controller 10 performs the above-described step (4c) to transfer data related to booting through the node connection unit 15 to another node. If not, select the clock transmitted from the node connected to the second node through the node connecting unit 15 through the node connecting unit 15 in step (4h) and perform step (4f) again to perform data related to booting from another node. To receive the boot.

Therefore, when the distributed node switching system is initially operated, the control unit 10 in each node checks whether the hard disk 16 is mounted in its own node and checks whether the self-booting is possible, and then selects self-synchronization when the self-booting is possible. If booting is not possible and self booting is impossible, SYNC_SEL_DB, which is boot related data transmitted from the first connection node of the adjacent node, is received, and the clock supplied from the connection node of the link corresponding to the value of F-PRMLNK or F-SNDLINK is received. It will boot by selecting it as the synchronization source.

If a failure occurs in the clock source output from the clock unit 11 of each node in the state where the distributed node switching system shown in FIG. 1 is operated by the booting as described above, the failures are illustrated in FIGS. 5A and 5B. It is automatically restored by the operation of the control unit 10 performing the same routine. 5A and 5B are interrupt routines that are operated at predetermined intervals.

The controller 10 executes the routines of FIGS. 5A and 5B in response to an interrupt signal generated at a predetermined cycle to process a clock error during system operation. See FIG. 5A and 5B for the operation thereof. When described in detail as follows.

First, when an interrupt signal is generated, the controller 10 accesses data of F_PRMSTS and F_SNDSTS in SYNC_SEL_WA as shown in FIG. 3B in step 5A (5a), reads the state of the clock synchronization source, and reads the current clock in step (5b). A comparison is made to see if it is the same as the clock synchronizing state output from the section 11.

As a result of the comparison in step (5b), when the state of the two synchronization sources is the same as the present state, the controller 10 determines that there is no error in clock synchronization and ignores it. However, if it is determined that the state of the synchronization source read from the clock unit 11 and the state of the synchronization source stored in the F_PRMSTS, F_PRMSTS and F_SNDSTS in the SYNC_SEL_WA are different from each other in step 5A of FIG. 5A, the control unit 10 determines the clock source. It is determined that abnormality has occurred. In step 5b, the control unit 10 determines that an abnormality has occurred in the clock source in step 5b. In step 5c, the controller 10 reads the contents of SYNC_SEL_DB indicated by F_SYNC_PTR as shown in FIG. That is, it checks whether there is a source to be read by reading the information of the SYNC_SEL_DB indicated by its F_SYNC_PTR and the state information of the synchronous clock sources of the first and second node connections corresponding thereto. If it is determined that there is a source to be replaced in step 5c of FIG. 5A, the controller 10 jumps to step 6a of FIG. 5, and if there is no clock source to replace, in step 5d of FIG. It is checked whether the fault clock source is a synchronous clock source with reference to F_SYNC_PTR and SYNC_SEL_WA shown in FIGS. 3A and 3B.

If it is determined that the current synchronization clock source is the fault source in the search of FIG. 5A (5d), the controller 10 performs step (6a) of FIG. 5b, and if it is not the fault source, the source state is changed in step (5e). Change it and store the contents in SYNC_SEL_WA as shown in FIG. The controller 10 masks the failure source to the SYNC_SEL_WA in step 5f and transmits the changed source status message to all nodes through the node connection unit 15 in step 5g.

If there is a source to be replaced in steps 5c and 5d of FIG. 5A, or if the fault clock source is the current clock source, the controller 10 jumps to the 5B degree and processes a clock error. At this time, when a failure occurs in the synchronization source, the controller 10 varies processing depending on whether the node to which the node belongs is a master node or a slave node.

If a failure occurs in the current synchronization source, the controller 10 reads F_MS of SYNC_SEL_DB0 set as shown in FIG. 3A at step 5B (6a) and checks whether it is a master node. If it is determined that the master node is its own master node in step 5B (6a), the controller 10 controls the clock unit 11 to select its own clock in step (6b). Follow the steps. The controller 10 performing step (6c) of FIG. 5B obtains the next master node with reference to the next SYNC_SEL_DB1 shown in FIG. 3A, changes it to the content of the next SYNC_SEL_DB1, and then, in step (6d) Check if it is a master node.

When the search result of step 5d (6d) determines that the master node is the master node, the control unit 10 transmits a clock synchronization source change message to all nodes through the node connection unit 15 in step 6f. Perform an operation to select the synchronization again. In this case, the reason for transmitting the clock synchronization source change message to all nodes is that the synchronization of the distributed node exchange is operated in synchronization with the clock of the master node, so that the change of the clock source of some nodes of all nodes affects the whole system. to be. Therefore, the clock synchronization between all nodes needs to be realigned.

The control unit 10 performing the step (5f) of FIG. 5B delays a predetermined time for processing the message sent to the slave node in step (6g), and in step (6h) the value of SYNC_SEL_DB as shown in FIG. The indicating one increments F_SYNC_PTR. As described above, the controller 10 which has changed the value of F_SYNC_PTR_ immediately selects the synchronization source according to SYNC_SEL_DB by controlling the clock unit 11 in step 6i. If it is determined in step 5d that the self is not the master node in step 6d, the control unit 10 transmits that the clock source is changed by transmitting a synchronous clock change message to the master node in step 6e.

On the other hand, if a master node change message transmitted from another node is received through the node connection unit 15 (FIG. 5B, step 6i), the control unit 10 performs the synchronization source change message to the slave node by performing the above-described step (6f). send. When the synchronization source change message is received from another master node (step 6k in FIG. 5B), the control unit 10 performs the above-described step (6h) to change the table data in FIG. 3 to reselect the synchronization source.

As described above, the present invention can more flexibly control each clock synchronization source to facilitate communication between nodes in a distributed node exchange system composed of multiple nodes, and when a clock error occurs, a synchronization source change message between nodes. By changing the synchronization source automatically by sending and receiving a signal, the system can be more reliable.

Claims (3)

A clock unit 11 which generates its own clock and selects one of the clock synchronous sources input in response to the synchronous clock selection control and outputs the synchronous clock, and the master slave information of the current node and the synchronous clock source connection node unit. A memory unit 12 having a first information area having information, a second information area having state information of the clock source node connection unit for synchronization of each node stored in the first information area, and data and clock sources between nodes; And a node connection unit 15 which checks the state of the clock synchronization source from the outside and outputs corresponding information, and selects a clock source from the node connection unit 15 by a predetermined control, and then the clock unit 11 is selected. Information of the subscriber unit 14, the hard disk 16 storing system program data, and the system program data and the memory 12, In the clock synchronization control method of a distributed node switching system having nodes composed of the control unit 10 for controlling the operation of each unit, Boot state search process for searching whether the hard disk is possible by searching for the presence of the hard disk, A first synchronous clock source selection process of selecting a self-clock in the clock unit as a synchronous clock in response to determining that booting is possible in the booting state searching process, booting according to the system program after selecting the clock source, and a distributed node In the second synchronous clock source selection process of selecting a clock source for switching system synchronization and the booting state search process, when it is determined that booting is impossible, a clock request message is transmitted by selecting a clock source of a neighboring connection node. The second boot after receiving the system program data transmitted from the node to boot the system Clock control method of a distributed node switching system, characterized by the outer boot constituted by any process running clock source selection process. The external booting process of claim 1, wherein the external booting process comprises: a third synchronous clock source selection process of selecting a clock source of a first node connection unit, a boot request message to another node through the node connection unit, and in response to the other node; A search process for checking whether a boot is possible by analyzing a response message transmitted from the system; a system boot process performed from the second synchronous clock source selection home when it is determined that booting is possible in the search process; and booting in the search process And determining the clock source of the next node connection unit and repeating the search process. A clock unit 11 which generates one's own clock and selects one of the clock synchronous sources input in response to the synchronous clock selection control and outputs the synchronous clock, and the master / slave information of the current node and the synchronous clock source connection node. A memory unit 112 having a first information area having sub-information, a second information area having state information of each node synchronization clock source node connection unit stored in the first information area, and data and a clock source between nodes. The node connection unit 15 for interfacing and checking the state of the clock synchronization source from the outside and outputting corresponding information, and the clock source 11 by selecting a clock source from the node connection unit 15 under predetermined control. Information of the subscriber unit 14, the hard disk 16 storing system program data, the system program data, and the memory unit 12, In the clock synchronization control method of a distributed node switching system having nodes composed of the control unit 10 for controlling the operation of each unit, the synchronization error detection to detect the presence of an error by searching the state of the current synchronization source at a predetermined period And an alternative source searching step of searching for the presence or absence of a source to be replaced by accessing the information of the first information area when detecting an error of the synchronization source, and the second source when determining that there is no alternative source in the alternative source searching step. A clock in response to determining that the fault source is not the current sync clock source during the clock state search process; Change the source status to mark source change information and fault source in the second information area, and transfer the change source status message to all nodes. If it is determined that there is an alternate source in the error source path process and the alternative source search process, or if the fault source is the current synchronization source in the clock state search process, it is searched whether it is a master node as the data of the first information area. In the first node operation state search process and the node operation state search process, if it is determined that it is a master node, it selects its own clock and then obtains the next master node. In the second node operating state search process for searching whether the master node of the second node operating state search process, and if it is determined that the master node is not the master node, and transmits a synchronization source change message to the master node, the master node At the same time, the synchronization source change message is transmitted to all nodes through the node connection unit. Changes and how the clock synchronization control in a distributed node switching system, characterized by synchronizing a clock constituted by any selection process of selecting the synchronization source.